SU1262511A1 - Interface for linking two electronic computers - Google Patents

Abstract

DEVICE FOR COUPLING TWO electronic computer (PC), comprising two front-end unit, each of which includes a transceiver amplifier node deschifrator control signals deschifrator addresses, register states, the switch, the register output data, wherein the trunk group of inputs-outputs The node of the transceiver amplifiers of each interface unit is connected to the information inputs-outputs of the corresponding computer, a group of information outputs, a group of state outputs, a group of address outputs and groups and the control outputs of the transceiver amplifier unit are connected respectively to the information inputs of the output data register, the status register, the address decoder and the control signal decoder, and the switch output and control decoder groups are connected to the information transducer amplifier and control input groups, respectively , the first, second and third outputs of the decoder control signals are connected respectively to the clock inputs of the output data register, the switch and the status register, the address of the address decipher is connected to the gate of the decoder of the control signals, the output of the identification of the register of the state register is connected to the information input of the switch, the outputs of the register of the data output are connected to the first group of information inputs of the switch, characterized in that the reliability of information exchange between EVL; an input data register and two groups of bus drivers are entered into each interface unit, the outputs of the output data register are connected to by the input inputs of iiniH shapers of the first group, the outputs of which are connected to the second group of information inputs of the switch, the fourth output of the decoder of control signals connected to the control inputs of the bus drivers of the first group, the outputs of the bus drivers of the second group are connected to the corresponding information inputs of the input data register, you (L which moves are connected with the third group of information inputs of the switch and with the corresponding information inputs of the bus drivers second groups, the fifth output of the decoder of control signals of one interface-1 block is connected to the input gateway of the state history hub and the synchronous input of the O5 register of input data of another interface block N71 C71, the outputs of the bits "transmission error and readiness of the exchange of the register of one interface block The transmission error and the readiness to exchange the state register of another interface unit are connected respectively to the inputs of the bits; the fourth output of the decoder of the signals of one interface unit is connected to channeling yuschimi inputs P1INNYH formers of the second group of other interface unit, input-output bus drivers of the first and second groups of one interface unit connected to the inputs-outputs of the bus drivers of the first and second groups of another interface unit.

Description

The invention relates to computing and can be used in computing systems.

The aim of the invention is to increase the reliability of information exchange between computers.

The drawing shows the block diagram of the device.

The device contains the first and second interface blocks 1 and 2, each of which includes a node of transceiver amplifiers 3, a decoder 4 controls, their signals, an address decoder 5, an output data register 6, a status register 7, a switch 8, an input data register 9, groups of bus formers 10 and I. The device also contains inputs-outputs 12-19 of the interface units, bidirectional tires 20 and 21 - data buses. Interface units 1 and 2 are connected respectively to the computer 22 and 23.

The exchange of information between computers is carried out in software mode and includes an address cycle and a cycle of receiving or transmitting data.

On the computer side, in each interface unit, the programmatically accessible are the status register 7, the output data registers 6 and 9. When reading information from register 9 in the monitoring mode, the bidirectional bus drivers 10 and 11 are respectively included in the monitor and the information stored in the input data register 9 is read into the computer that has written the information register.

To access any of the registers, the computer in the address cycle of the operation places the address of the required register, the high-order bits of which indicate that this address belongs to the address area of the interface unit, which includes the register, and the lower-order bits - to the specific register that is being accessed. If the addresses of the decoder 5 correspond to the address, the computer outputs to the decoder 4 control signals a device sampling signal.

The decoder 4 control signals selects the required register of the interface unit and, depending on the type of operation performed by the computer, either writes information to the selected register or reads data from it.

The decoder 4 control signals also provides a sync signal to the computer, allowing the machine to judge the correctness of the cycle of access to the device.

The device works as follows

When the power is turned on or the initial setup signal arrives at the interface units 1 and 2 from the computers controlling them, the state registers 7 of each

interface blocks 1 and 2 expose the outputs of the readiness of the interface blocks at the outputs 16 to receive information; from the output 16 of one interface block, the readiness signal is fed through inputs 17 to the 7 state register of the other interface block.

If necessary, for example, to transfer the information word from the computer 22 to the computer 23, the control program of the computer 22 polls the 7 state register of the interface unit 1 and analyzes it for the presence of an output readiness signal. In the case of the presence of such a signal, the computer performs an operation of recording information in the output data register 6. This information is fed to the information inputs of the bus drivers 10 of the first group and, since at its control input the signal "Read control information is absent, is transmitted to the second bidirectional data bus 21 of the first interface unit and the first bidirectional data bus 20 of the second interface unit.

Since the signal "read control information on the control inputs of the bus driver 11 of the second group of the second interface unit is missing, the information received on the first bidirectional bus 20 data will be transmitted respectively to the inputs of the input data register 9 of the interface unit 2. Recording information The input data register 9 of the interface unit 2 will be transmitted according to the gating signal supplied to the input 12 of the interface unit 2 from output 13 of the decoder 4 of the interface unit 1.

The control program of the computer 23 polls the 7 state register of the interface unit 2 and analyzes it for availability (Signal "Readiness input. With such a signal, the computer 23 performs an operation of reading information from the input data register 9 of the interface unit 2. Performing a read operation from the data register 9 the input causes the reset of the readiness to input the register 7 of the interface unit 2 and the installation of the ready signal at the output 16 of this block, which, at the input 17 of the interface block 1 and then into the state register 7, can be read from ud computer 22 as the output signal of readiness.

Next, the computer 22 can again carry out the transfer of the word information in the computer 23.

In case the computer 22 needs to be convinced of the correctness of the information transmitted to the computer 23, i.e. in fact, the one that was recorded in the register 9 of the input data of the interface unit 2 and then read from there to the computer 23. The computer 22 performs an operation of reading information from the register 9 of the interface unit 2, in which the decoder 4 generates the signal "Read control information input inputs of bus formers 10 of the first group, output 18 of interface unit 1, inputs 19 of interfacial unit 2 and control inputs of community drivers 11 for the second group of interface unit 2. This signal changes the direction of transmission These data sources and information from the output of the register 9 of the input data of the interface unit 2 are fed to the input of the switch 8 of the interface unit 1 through the field supply drivers 11 of the interface unit 2 and bus drivers 10 of the interface unit 1, and then through the node of the transmit-receive amplifiers 3 in the computer 22. Last compares the information read in this way from register 9 of input data with that which was written there. If the information of the computer 22 coincides, it can continue the exchange with the computer 23. If a discrepancy is found between the information received and the one that was recorded, the computer 22

sets to "1 bit" The transmission error in the 7 register of the interface unit 1 and the output 14 of the interface unit 1 shows the "Transmission error" signal, which is fed to the input 15 of the interface unit 2 and then to the 7 state register.

When reading in the register of 7 states of the single bit “Error of transmission of the computer

23 depending on the control program algorithm, it can either stop the execution of the current program and issue a malfunction message, or wait for a second message in order to put the newly received information instead of the false information. The computer 22, having transmitted an error message to the computer 23, depending on the control program algorithm, can either stop the execution of the program and issue a malfunction message, or wait for

signal "readiness output, repeat the parcel.

Claims (1)

A DEVICE FOR PAIRING TWO ELECTRONIC COMPUTING MACHINES (COMPUTERS), containing two interface units, each of which includes a node of transceiver amplifiers, a decoder of control signals, an address decoder, a status register, a switch, an output data register, and a trunk group of inputs and outputs of the node transceiver amplifiers of each interface unit is connected to the information inputs and outputs of the corresponding computer, a group of information outputs, a group of status outputs, a group of address outputs and a control group the most important outputs of the transceiver amplifier node are connected respectively to the groups of information inputs of the output data register, status register, address decoder and decoder of control signals, and the output group of the switch and the decoder of control signals are connected respectively to the groups of information and control inputs of the transceiver amplifiers node, the first, second the third outputs of the control signal decoder are connected respectively to the sync inputs of the output data register, the switch, and the register with status, the output of the address decoder is connected to the gate input of the decoder of the control signals, the output of the status register identification bit is connected to the information input of the switch, the outputs of the output data register are connected to the first group of information inputs of the switch, characterized in that, in order to increase the reliability of the exchange of information between A computer, an input data register and two groups of bus drivers are introduced into each interface unit, the outputs of the output data register being connected to the information inputs of other formers of the first group, the outputs of which are connected to the second group of information inputs of the switch, the fourth output of the decoder of control signals is connected to the control inputs of the bus formers of the first group, the outputs of the bus formers of the second group are connected to the corresponding information inputs of the input data register, the outputs of which are connected to the third group of information the inputs of the switch and with the corresponding information inputs of the bus formers of the second group, the fifth output is a decoder and the control signals of one interface unit are connected to the gating input of the status register and the sync input of the input data register of another interface unit, the outputs of the bits “transmission error” and “Readiness of exchange” of the status register of one interface unit are connected respectively to the inputs of the bits “Transfer error” and “Readiness of exchange "The status register of another interface unit, the fourth output of the decoder of the control signals of one interface unit is connected to the control inputs of the bus drivers Torah group other interface unit, inputs and outputs of the bus drivers of the first and second groups of one interface unit connected to the inputs-outputs of the bus drivers of the first and second groups of another interface unit. Yu N3 SI