SU1624468A1 - Device for interfacing two digital computers - Google Patents

Abstract

The invention relates to computing and can be used in multi-machine computing systems for communication of digital computers. The aim of the invention is to increase speed. The device contains two communication units, a command comparison unit, a mode setting unit and a buffer register. 6 Il.

Description

The invention relates to computing and can be used in multi-machine computing systems for communication of digital computers.

The aim of the invention is to increase speed.

In figure 1, 2 shows the block diagram of the device; FIG. 3 is a functional block diagram of the mode setting; FIG. 4 is a functional diagram of the firmware control node; FIG. 5 is a graph of the microprogram control node algorithm; Fig. 6 is a functional diagram of a buffer memory node.

The device contains (Figs. 1, 2) first and second communication blocks 1 and 2, each of which contains node 3 receivers, register 4 commands, decoder 5 commands, address register 6, address comparison node 7, firmware control node 8, node 9 transmitters, register 10 byte status. In addition, the device contains a buffer register 11, a command comparison block 12, a mode setting block 13, inputs 14-17, outputs 18-21.

Each of the communication units with the channel contains a buffer memory node 22 with information inputs 23 and outputs 24, second 25 and first 26 synchronous inputs, outputs 27.

The mode setting unit contains (FIG. 3) a switch node 28 and a switch 29.

Firmware control node 8 (FIG. 4) contains an input multiplexer 30, a fixed memory 31, an output register 32. FIG. 4 also shows the input 33 of the synchronization signals and the input 34 of the initial setup.

Multiplexer 30 is designed to implement conditional transitions. Permanent memory 31 serves to store a set of microinstructions. Output register 32 is designed to eliminate the variation in sampling time of different address bits of the fixed memory. The information inputs of the multiplexer are connected to the inputs of the node, through which the signal of the transition from one state of the node 8 to another enters. The output of the multiplexer is connected to the lower address input of the fixed memory 31, to the group of address inputs of which are fed

"G

Yo

ABOUT

Yu

I

about with

signals from the output register. Node 8 is implemented as a firmware automaton whose graph-algorithm is presented in Fig. 5 (for simplicity, a part of the algorithm describing the operation of Write One Memory mode is given. firmware). This box shows the address of the memory location in which the microinstruction is stored in circles; arcs depict transitions from one state to another-1. The names of the signals are formed in these states; the transition from one state (the beginning of the arc) to another (the arrow of the arc) occurs when this signal is present.

The buffer memory nodes 22 (Fig. 6) contain a memory 35, an address counter 36, a byte register 37, and a comparison node 38.

In the Single Memory mode, the device operates as follows.

The DVR channel (for example, the first one) selects a device in accordance with the principles of organizing the evodee output of the EU-computer interface. At the same time, the address from the channel on busses 14 of the channel, via node 3, goes to node 7 for comparison with the address of the adapter stored in the address register. The result of the comparison of addresses is given to node 8. If the addresses match, from node 3, the address of the adapter of the Tripoli passes through node 9 to output 18 and then to the analog.

The decoder 5 decodes the command received from the channel and stored in register 4.

Pie ie decrypt the command of the first channel and determine the mode of operation by the command code or the state of the node 28 of the block

13 device receives at the entrance

14 and recording information through node 3 into node 22 of block 1. With this, node 8 of block 1 generates a zero signal, and then signals from counter 36 and return signals to memory 35, which are fed to the recording control inputs of block 22 of block 1.

After the end of data reception from the first channel (the end is determined by the channel, unit 8 of the block 1 generates a signal of the Record about the register 37, which arriving at the recording control inputs of the node 22 of the block 1, writes the register of the first channel to the register 11, and the node 8 of the block 2 generates and transmits At the second channel, the status byte with the pointer is Attention. In response, the second channel enters a command to refine the state on which the contents of register 11, i.e. / command of the first channel, are transmitted. According to the contents of register 11, the program of the second CVM determines which command is needed enter it into the device and enter it into the device through the second channel.When the commands are compared by block 12 (modifier fields are compared), the device starts to transmit data from node 22 of block 1 through node 9 of block 2. In this case, node 8 of block 2 generates zero signals neither, and then the signals of modification of the counter 36 and the signals for accessing the memory 35, which are fed to the read control input of the node 22 of the block 1.

When comparing the value of counter 36 and

5 of register 37, which indicates that the transmission to the second channel of data received from the first channel is completed, the output from the comparison node 38 is generated from the synchronization output of node 22

0 of block 1 to node 8 of block 2. by which the execution of a command in the second channel ends.

When transmitting data from the second channel, the first device also works except that data is recorded in

node 22 of block 2, writing to node 22 controls

node 8 of block 2, and reading - node 8 of block 1.

In Dual Memory mode

provides simultaneous reception of data from the first and second channels to nodes 22, respectively, blocks 1 and 2, or transfer to the first and second data channels from nodes 22, respectively, blocks 2 and 1.

In this mode, if both channels transmit data to the device at the same time, the data of the first channel are recorded in the node 22 of block 1, and the data of the second channel are recorded in the node 22 of block 2. Then the second channel transfers byte through the register 11 and the node of block 2

0 states with a pointer Attention, after that the status byte with the pointer pointer is transmitted to the first channel through register 11 and node 9 of block 2, then to the first channel through register 11 and node 9 of block 1

5, the same byte is transmitted. The programs of the first and second digital computers enter into the device commands of the state refinement, determine the necessary response commands and enter them through the first and second channels into the device.

0 By these commands, data from node 22 of block 1 is transmitted to the second channel, and data from node 22 of block 2 to the first channel. In this mode, block 12 does not work and command comparison is not performed. Nodes 8 according to the signals of the command decoder 5 will only analyze the direction of data transmission (write or read command). The actual writing and reading procedures at nodes 22 are performed in the same way as in the One Memory mode,

This device differs from the prototype device by setting the operation mode using the toggle switches of the switch node of the mode setting unit 13 and the value of the corresponding bits in the command format.

The device operation modes are defined by block 13. In this device, there are three ways of setting modes, determined by the position of the corresponding toggle switches of node 28, namely: operational control by the commands of the first channel (through switch 29 to the inputs of nodes 8, the corresponding bits of command register 4 of block 1 are transmitted communication with the channel); operational control by commands of the second channel (bits of the command received from the second channel are transmitted through the switch 29); non-operational management (as well as in the device of the prototype - tokens of node 28).

Firmware control unit 8 operates as follows.

In the initial state, the registers 32 are set to zero, and the zero-address address is present at the address inputs of the permanent memory 31. After resetting the initial setup signal, for each synchronization signal, an analysis of the condition signals arriving at the inputs of the multiplexer 30 and the transition to the next state is performed. In each state of node 8, one of the input buses of the node is connected to the address input of the fixed memory 31. The selection of a plug-in bus is made in the microcommand format field.

Possible format of micro-commands is

L

AMK

AMX

UIR

where AMK is the address field of the following microcommand;

АМХ - code field of the address of the connected input of the multiplexer;

UPR is the output field of the control device.

If an input signal is present on the input bus (i.e., log. 1), then node 8 enters a state in the lower order of which there is one. If there is no input signal on the selected bus (i.e., there is a log. O), then the automaton goes into a state where there is a zero in the lower order. For example, let the constant memory address field 31 represent combination 0011, the address field of the input multiplexer 30 be 0101. If at the fifth input of the multiplexer 30 (corresponding to code 0101) there is an input signal (i.e. a log. 1), then the transition

performed at address 00111; if there is no input signal, at address 00110.

Similarly, all other conditional transitions are implemented.

5 To generate output signals

control devices use horizontal firmware, i.e. Each bit of the field of the microcommand output signals corresponds to the determined output of the control device.

Claims (1)

Claim device for interfacing two digital computers 15 containing a command comparison block, a mode setting block, a buffer register, two communication blocks, each of which contains a receiver node, a transmitter node, an address register, a command register, an address comparing node, a command decoder, a firmware control node, a status byte register , a buffer memory node, the information inputs of the receiver nodes of the first and second communication units being the device inputs for connecting respectively to the information outputs of the first and second digital computers, information outputs of the transmitter nodes The first and second communication units are 0 outputs of the device for connecting respectively to the information we enter the first and second digital computers, the first inputs of the power / current condition and the first outputs of the microprogram control nodes of the first and 5, the second communication units are the inputs and outputs of the device for connecting, respectively, to the command outputs and inputs of the first and second digital computers. while the information outputs of the command registers 0 of the first and second communication units are connected respectively to the first and second information inputs of the command comparison unit and the mode setting unit, the output of the command comparison unit is connected to the second inputs of the logic condition of the first and second communication unit microprogram control units, the first and second operation mode outputs the mode setting unit is connected to the third inputs 0 logical condition of the firmware control nodes of the first and second communication units, the second outputs of the nodes. The program control of the first and second communication units is connected to the first one respectively. 5 and the second synchronized inputs of the buffer register, the information output of which is connected to the first information inputs of the transmitter nodes of the first and second communication units, the information outputs of the receiver nodes of the first and second communication block connected to the first and second information inputs of the buffer register, respectively; the first information outputs of the buffer memory nodes of the first and second communication blocks are connected to the second information inputs of the transmitter nodes of the second and first communication blocks, respectively, the first synchronous inputs of the buffer memories of the first and second blocks zi are connected to the third outputs of the microprogram control units of the second and first communication units, respectively, the second information outputs of the first and second buffer memory nodes The communication units are connected to the fourth inputs of the logic condition of the microprogram unit nodes of the second and first communication units; the input / output of the logic condition of the microprogram control unit of the first communication unit is connected to the input-output of the logic condition of the microprogram unit ddMMHoro control of the second communication unit, and in each communication unit the information output of the address register is connected to the first information input of the address comparison node, the second information input of which is connected to the third information input house of the transmitter node, with the information input of the buffer memory node, with the information output of the receiver node and with the information input of the command register, the information output of which is connected to the information input of the command decoder, the output of which is connected to the fifth input of the logic condition of the microprogram control node, the fourth output connected to the control input of the address comparison node, the output of which is connected to the sixth input of the logic condition of the firmware control node, the fifth output of which is with information the input of the status byte register, the information output of which is connected to the fourth information input of the transmitter node, the fifth information input of which is connected to the sixth output of the node firmware control, the seventh and eighth outputs of which are connected respectively to the synchronized input of the command register and the second synchronized input of the buffer memory node, while the task block Modes contains a switch node, characterized in that, in order to improve speed, a switch is entered in the mode setting block, with the first and second information inputs and the information output of the switch are the first and second information inputs, the first and second outputs of the unit operation mode, respectively, and the first and second The second outputs of the switch node are connected respectively to the third information input and the control input of the switch. go 18 Phie 1 FIG. 2 from registers 4 b / 1ok8181 3L W D2 DJ to nodes 8 blocks 1 and 2 Fig.Z nineteen 21 P i & f §s | Hey g tat § | SI " en