SU1305697A2 - Channel-to-channel adapter - Google Patents

Abstract

The invention relates to computing and can be used in multi-machine computing complexes for communication of digital computers. The purpose of the invention is to increase the performance of the adapter. The channel-channel adapter contains the first and second blocks 1 and 2 of communication with the channel, each of which has a node 3 output signals, a register of 4 commands, a decoder 5 commands, a register of 6 addresses, a node 7 of comparison, addresses, a node 8 of control, a node 9 output signals, register 10 bytes of status. Blocks 1 and 2 of communication with the channel are interconnected by several control lines and 00 о 01 Oi with N)

Description

through the common buffer register 11, the command comparison block 12 and the mode setting block 13. The adapter is connected to the mating channels with reference 14 and

15 information lines of channels, tires

16 and 17 control lines of channels, tires 18 and 19 information LINIRG subscribers, tires 20 and 21 control lines of subscribers. Each of the units 1, 2 of communication with the channel contains a node 22 of the buffer memory, including switches of control signals for writing and reading, input information, a counter

one

The invention relates to computing, can be used in multi-machine computing complexes for the communication of digital computers (DVM) and is an improvement to the device according to the author. No. 1049895.

The purpose of the invention is to increase the performance of the adapter.

Fig. 1 is a block diagram of an adapter; Fig. 2 is a functional node of a buffer memory; Fig. 3 shows a functional diagram of the control unit; Fig. 4 shows a state and transition graph of the control unit.

The dapter contains (Fig. 1) the first and second blocks t and 2 links to the channel, each of which includes a node 3 output signals, a register of 4 commands, a decoder of 5 commands, an address register 6, an address comparison node 7, a control node 8, node 9 output signals register 10 byte status.

Blocks 1 and 2 with a connection to a channel: between them are the control lines and through the common buffer register 11, the command comparison unit 12 and the mode setting unit 13. The adapter is connected to the associated channels via 4 buses to 15 information lines of channels 16 and 17 control lines of channels, buses 18 and 19 subscriber information lines, buses 20 and 21 control 1G (shs subscriber lines).

Each of blocks 1 and 2 contains a buffer memory node 22 with the first information input 23 and output

addresses, byte count, memory, comparison circuit, OR element. Control node 8 has an input multiplexer, a persistent memory, an output register. The essence of the invention is to make it possible to use the total amount of memory and buffer memory nodes for transferring large amounts of information on a single command, which reduces the time spent on establishing communication with channels and improves the performance of the adapter and the computing complex as a whole. 4 il.

five

five

five

0

24, the first control inputs of record 25 and read 26, the control input 27, the second information input 28, the second control inputs of record 29 and read 30.

The buffer memory node 22 contains (FIG. 2) control switches of the write 31 and read 32 signals, the input information switch 33, the address counter 34, the byte number register 35, the memory 36, the comparison circuit 37, and the OR element 38.

The control unit 8 comprises an input multiplexer 39, a permanent memory 40, an output register 41. FIG. 3 also shows a sync signal bus 42, an initial installation bus 43, and an input and output bus 44-57 of node 8.

Multiplexer 39 is designed to implement conditional transitions. Permanent memory 40 serves to store a set of micro-instructions. Output register 41 is designed to eliminate the sampling time of different addressable bits of the fixed memory.

The information inputs of the multiplexer 39 are connected to the input buses of the node, through which transition signals from one state of node 8 to another are received. The output of the multiplexer 39 is connected to the lower address input of the permanent memory 40, to a group of address inputs that are supplied with signals from the output register.

Node 8 is implemented in the form of a firmware automaton whose graph-algorithm is presented in FIG. A part of the algorithm describing the execution of the operand Recording in the Expanded Memory mode is given. The remaining parts of the algorithm are done in a similar way. Each part of the algorithm can be executed as a separate firmware. In the column of FIG. A, in the circles, the address of the memory cell 40 is shown, in which the microinstruction is stored, the arcs are the transitions from one state to another, the names of the signals above the circles mean that the signals are formed in these states, The name of the signals above the arcs means that the transition from one state (the beginning of the arc) to another (the arrow of the arc) occurs when this signal is present.

Nodes 3 of the output signals are a group of amplifiers-receivers of interface signals and receive information signals of the interface from the channel via buses 14 (15)

Register 4 and decoder 5 commands receive, store and decrypt the code from the channel.

The registers 6 and the address comparison nodes 7 compare the address with the specified address entered into the channel and enter the channel with the specified address.

The control nodes 8 terminate internal control signals and control signals on buses 20 (21) subscriber control lines in accordance with the command code, signals coming from the channel through buses 16 (17) and signals of the mode setting unit 13

The output signal nodes 9 are interface amplifiers and transmit information signals to the channel on buses 18 (19).

A register of 10 status bytes is used to store and transfer status bytes to the channel. The formation of bits in the registers 10 is carried out on the signals of nodes 8.

The buffer register 11 receives, stores and transmits byte commands and data to the channel. Broadcast

data through register 4 is performed only in modes in which the buffer memory nodes 22 are not used.

Block 12 compares the codes of the commands received from the first and second channels. Block 13 is a toggle register that specifies five modes of operation: Monopole, Multiplex, One memory, Two memory, Spread memory. The buffer memory nodes 22 serve to receive, store, and transfer data bytes to the channel.

Adapter channel — the channel operates in five modes specified by block 13. In modes L, there are Onopole, Multiplex, One Memory, and Two Memory Adapters in the same way as the well-known adapter.

In the Expanded Memory mode, the proposed adapter operates as follows.

The channel (for example, the first) selects the adapter in accordance with the principles of the organization of input-output. The address from the channel bus 14 channel through node 3 enters the node

7dl compare with the adapter address stored in address register 6. The result of the comparison of addresses is given to node 8. If the addresses match, then from node 7 the adapter's reply address is sent to buses 18 and further to the channel.

The decoder 5 decodes the command received from the channel and stored in register 4.

After decrypting the command of the first channel, the adapter receives on buses 14 and writes through node 3 to node 22 of information block 1. At that, node 8 of block 1 generates a zero signal, and then signals of modification of counter 34 and reference signals to memory 36, which are fed to inputs 25 of node 22 of block 1.

After the total memory of the memory 36 is filled, the counter 34 generates an overflow signal, which through the OR 38 element goes through the bus 27 to the node

8blocks 1. By this signal, node 8 of block 1 continues to record information at node 22 of block 2. At the same time, information on buses 28, recording control signals on buses 29 goes to node 22 of block 2 from node 8 of block 1.

After the end of reception from the first data channel (the end is determined by the channel), unit 8 of block 1 generates a write signal to register 35, which is fed to inputs 29 of node 22 of block 2, writes the command} }iorc to the register 11, and node 8 of block 2 generates and sends to the second channel the status byte with the Attention pointer. In response, the second channel inputs a state refinement command, through which the contents of register 11 are transmitted to it, i.e. first channel command. According to the contents of register 11, the program of the second digital computer determines which command must be entered into the adapter, and through the second channel enters it into the adapter. When comparing commands by block 12 (modifier fields are compared), the adapter starts transmitting data from node 22 of block 1 to node 2 through node 9 of block 2. At the same time

node 8 of block 2 generates a signal

zeros, and then the modification signals of the counter 34 and the signals to the memory 36, which are fed to the inputs 25 of the node 22 of the block 1.

After reading the entire volume of the memory 36, the counter 34 generates an overflow signal, which through the OR element 38 through the bus 27 enters the node 8 of block 2. By this signal the node 8 of block 2 continues reading information from the node 22 of block 2 and transmitting it to the second channel node 9 of block 2 At the same time, the read control signals to node 22 of block 2 are fed along buses 30 from node 8 of block 2.

When comparing the value of counter 34 and register 35, which indicates the completion of the transmission to the second channel of data received from the first channel, the output of the comparison circuit 37 is a signal arriving through the OR 38 element from the code 27 of the node 22 of the unit 2 to the node 8 block 2, on which the execution of a command in the second channel ends.

Switches 31,32 and 34 provide switching of control signals for writing and reading information received at the inputs of node 22 either from block 1 or from block 2 (from the outputs of node 8 and node 3).

When transferring data from the second channel to the first adapter, it works the same way, except that the information is recorded first in node 22 of block 2, and then in node 22 of block 1 under the control of node 8 of block 2, and read from the node 22 block KZ 2, and then from the node 22 of the block 1 under the control of the node 8 of the block 1.

The control unit 8 operates as follows.

In the initial state, the reg ister 4 is reset and there is a zero address on the address inputs of the permanent memory 40. After resetting the initial setup signal, for each synchronization signal on the bus 42, an analysis is made of the condition signals received at the inputs of the multiplexer 39, and the transition to the next state.

In each state, node 8 connects one of the input buses of the node to the address input of the permanent memory 40.

The selection of a plug-in bus is made in the microcommand format field.

The possible microcommand format has the following form:

AKH

UIR

where AMK is the address field of the following microcommand;

AMX - the code field of the address of the connected input of the multiplexer,

UPR is the output field of the control device. If an input signal is present on the output bus (i.e., logical 1), then node 8 enters a state in which the one is present. If there is no input signal on the selective one (i.e., there is a logical O), then the automaton goes into the state, in the lower order of which there is zero.

For example, let the address field of permanent memory 40 be a combination of 0011, the address field of the input multiplexer 39 is 0101. If the input signal (i.e., logical 1) is present at the fifth input of multiplexer 39, then the transition is performed at address 00111, if the input signal is absent at address 00110. All other conditional transitions are implemented in the same way.

To generate the output signals of the control unit, horizontal microprogramming is used, i.e. Each bit of the field of the microcommand output signals corresponds to a certain output signal of the control device.

Claims (1)

Formula Fig. eteny Adapter channel - channel auth. No. 1049895, characterized in that, in order to increase the performance of the adapter, the second information inputs and the write control inputs of the buffer memory nodes of the first and second communication blocks to the channel are connected respectively to the tenth outputs of the control nodes and the outputs of the input nodes of the second and first blocks communication with the channel in each In communication with the channel, the second read control input, the control output and the information output of the buffer memory node are connected respectively to the eleventh output and the eighth input of the control node condition and the sixth input of the output signal node. 2 Fig.Z "Slili P (2dakts p S.S.Pekar Compiled by V. Vertlib Tehred L. KravchukCorrector L.Patay Order 1 53/47 Circulation 673 Subscription BNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4