SU1265787A1 - Driver for multiplexor channel - Google Patents

Abstract

The invention relates to computing technology. The purpose of the invention is an increase in the utilization rate of equipment. The device contains a buffer register, subscriber identifier register, subscriber state fixing unit, channel identifier register, switch, descrambler, parity nodes, subchannel and subscriber address registers, memory block, status byte register, interrupt request register, triggers, elements AND, NOT. The device (provides for the combination of I / O operations in the processing of several / L ki interrupt. 1 Il.

Description

The invention relates to computing and can be used in the development of computer input-output channels. The purpose of the invention is to increase the utilization rate of the equipment. The drawing is a block diagram of the device. The device contains a buffer j register 1 of output information, register 2 of subscriber identifiers, block 3 of fixing the channel status, register A of channel identifiers, switch 5, element 6, element 6, OR 7, input register 8, the first parity control node 9, decoder 10, subscriber address register P, second parity node 12, subchannel address register 13, memory block 14, information register 15, interrupt request register 16, register 17 byte of state, block 18 combining the final state byte of devices input-output (external devices TV), additional element AND 19, two elements NOT 20 and 21, first trigger (address equality) 2 second trigger (subchannel occupancy) 23, comparison circuit 24, information input 25 channel, channel interface bus 26, interface subscriber bus 27, output 28 of the device. 1.g final setting interrupt type signal 29 device terminus signal, channel control identification lock signal 30 (UPRK), channel information identification signal 31 (INF-4), final device interrupt signal 32 end device, input device address 33 of the state byte sent, the inverse signal 34 of the subscriber operation ID (RAB-A) 34, the subchannel occupancy signal 35, the request register busy signal 36 for interruption, and the address 37 of the device making the interrupt request. The control unit for the multiplex channel contains a buffer register 1, the input of which is connected to the information input 25 of the channel, and the outputs are connected to the interface bus 26 of the channel and the first input of the input register 8, the outputs of which are connected to the inputs of the first parity node 9, the decoder 10 and with the first input of the register 17 bytes of the SDT, the interface bus of 27 subscribers is connected to the second input of the input register 8 and the inputs of the register 1 1 of the subscriber's address and register 2 of the subscriber's identifiers, the first output of which is connected to The first input of the channel state fixing unit 3, the second input of which is connected to the informational input 25 of the channel, and the outputs with the register input 4 of the channel identifier and the first input of the interrupt request register register 16, the first output of which is connected to the third input of the state fixing unit 3 channel, the output of the subscriber’s address register 11 is connected to the inputs of the second parity control node 12, the address register 13 and the second input of the interrupt request register 16, the second output of which and the output of the 17 byte register are the device output 28, the output of the address register 13 through the memory unit 14 connected in series and the information register 15 is connected to the input of the memory block 14, the outputs of the first 9 and second 12 parity check nodes and the first output of the decoder 10 are connected to the fourth input of the channel state fixing unit 3, the first and the second outputs of the register 4 channel identifiers are connected to the first inputs of the element AND 6 and element OR 7, respectively, the remaining outputs of the register 4 channel identifiers and the outputs of the elements AND 6, OR 7 are connected via switch 5 to the interface bus 26 la, i swarm vyhsUd secondary decoder 10 is connected to the input of the additional pervm AND gate 19, whose output is connected to the second input of the byte register 17 and the state through the first NOT element 20 to the input of AND gate 6 and a second NOT member 21, whose output is connected. with the input of the element OR 7, the output of the register 11 of the subscriber's address and the second output of the register 16 of the interrupt request are connected to the inputs of the comparison circuit 24, the output of which is connected to the first input of the first trigger 22, the output of which is connected to the second input of the additional element AND 19 the output of the information register 15 is connected to the first input of the second flip-flop 23, the output of which and the first output of the register 16 of the queuing request are connected respectively to the third and fourth inputs of the pre-control element And 19, the second output of the register 2 id ntifikatorov subscriber connected to the second inputs of the first 22 and second 23 flip-flops.

Register 2 of subscriber IDs 5 contains the following identification signals: subscriber operation (RAB-A), subscriber address (ADR-A), subscriber management (UPR-A), subscriber information (INF-A), subscriber sample (VBR-A ), subscriber data (DAN-A), subscriber requirement (TRB-A).

The channel state latching unit 3 interacts with input-output devices using an input-output interface signal sequence initiated by the channel or initiated by input-output devices according to the TRB-A.

Register 4 of channel identifiers contains the following identification signals: channel operation (RAB-A), channel sampling (VBR-A), channel address (ADR-K), channel control (UPR-K), channel information (INF-K), channel data (DAN-K).

The decoder 10 generates the signals of the final interruption of the type of the channel has finished, the device has finished.

Register 11 of the address of the I / O device serves to store the address of the external device that sent its address on the subscriber interface bus.

The subchannel address register 13 is intended to form the addresses of the memory cells for selecting the control units of the device words (UIC) forming the subchannel to the information register 15 from memory block 14.40

Register 16 request for termination (RZP) is used to store the address of the input-output device that sent the final status byte and has already received a request to the processor for processing this 45 byte.

The 17 byte state register is used to store the final state byte of the end channel type and may contain the following bits: attention, 50 modifier, control device finished, busy, channel finished, device ended, device failed, a special case.

Block 18 combining the final byte 55 of the I / O devices allows combining the two final bytes of the state of the end channel type and the device ended up in a single I / O command, which means that the two input / output interrupts will be processed by the processor as one g.ryvanie

The control unit for the multiplex channel, comprising a block combining the final status bytes of the input-output devices, works as follows.

The execution of an I / O operation in any subchannel is completed when the status byte of the channel has finished has been received from the external device. The device address from the subscriber address register 11 is entered into the interrupt request register 16 to be sent to the interrupt processing request to the processor, and the status byte of the end channel is entered into the 17 register of the status byte. The low-level memory signal is generated. If the processor is free at this moment, it processes this interruption, the interrupt request register is released. If the processor is busy, the interrupt is stored in the control device for the multiplex channel in registers 16 and 17. By this time, the input device can send byte-states like the device terminated, the TRB-A signal is sent to the interface bus 27 of the subscribers. In response, the channel state blocking unit generates and sets the trigger on the channel identifier register on the channel identifier register. The VBR-K signal via the interface bus 26 of the channel enters the input-output device. The device answers via the interface bus 27 subscribers, the identification signal RAB-A (register 2 subscriber identifiers) and the address of the device, which is entered in register 11 of the subscriber's address, accompanied by its identification signal ADR-A (register 2). The channel state fixing unit 3 removes a VBR-K signal from the register 4 of channel identifiers.

The address of the input-output device from the register 11 of the address of the subscriber and the address. the devices from the interrupt request register 6 that sent the interruption request are compared in diagram 24, sine. In case of comparison, set. is cast into the first trigger (address equality) 22.

The address of the I / O device in register 13 of the subchannel address is used to form the CSS address for the device. On the information register 15 for the analog device, a pair of the ACM is received, but which analyzes the subchannel occupancy (the eighth bit of the information register 15) and if the subchannel is occupied (communication 35), the second trigger 23 stores this state. If the subchannel is occupied, the HRC is occupied, which means that for a given external device in the control device for a multiplex channel, an interrupt of the type of channel terminated is stored (not yet processed).

And if the addresses were compared, it means that 15 in this sample by the TRB-A is represented the status byte of the device type ended. The channel state fixing unit 3 continues the device sampling according to the TRB-A, placing the UPR-K signal further on the register of 4 identifiers, indicating that the sequence of the sampling signals can be continued.

The I / O device resets the signal of the ADR-A identifiers (re. Register 2), in response, the channel state fixing unit 3 resets the signal of the LPRP-K (register 4).

Then, the I / O device sprinkles 27 interface 30 byte bus bytes on the interface bus, followed by its UPR-A identification signal (register 2). If the status byte contains only a bit, the device ends (the remaining 35 bits of the byte are zero), which determines. the decoder is 10, this means that the input-view ode command has been executed correctly, and the register 16 of the request for termination is-; nt, element 19 is triggered. Signal 40 from output 19 sets the final type bit of the device type ending in register 17 byte of status the end byte of the type of device terminated is connected to the stored state byte of the type ended channel the signal from the output NOT 20 blocks the signal of the UPR-K signal on element I 6 (the output of the UPR-K would mean to remember the distance 50 on the input-output device): the signal from the output NOT 21 through the element OR 7 exposes a signal to the interface bus of the channel Identification INF-K, which means for an external device -keeping, 55 bytes WHAT state type device received left off control device for multiplex channel.

B. Ostapnyh cases nlbyyt state of the device is finished but the external device is still on the UPR-A will receive a response UPR-K (fill the byte of the state on the external device). Having received the INF-K answer, the external device removes RAB-A. By removing RAB-A (subscriber identifier 2 register 2, link 34), triggers 22 and 23 are reset. Sampling on demand of the I / O device is completed. Subsequently, the combined final channel type terminations and the device ended will be processed by the processor as one I / O interrupt.

Claims (1)

Invention Formula A control unit for a multiplex channel containing a buffer register, whose input is connected to the channel information input, and the outputs are connected to the channel interface bus and the first input register register, the outputs of which are connected to the inputs of the first parity control node, the decoder and the first input of the status byte register , the subscriber interface bus is connected to the second input of the input register and the inputs of the subscriber address register and the subscriber identifier register, the first output of which is connected to the first input block the latching state of the channel, the second input of which is connected to the information input of the channel, and the outputs to the input of the channel identifier register and the first input of the request register register, the first output of which is connected to the third input of the channel state latching unit; with the inputs of the second node. the parity check, the address register and the second input of the interrupt request register, whose second output and the output of the status byte register are the output of the device, the output of the address register is connected to the memory input through serially connected memory and information register, the codes of the first and second nodes parity control and the first code of the decoder are connected to the fourth input of the channel state fixing unit, the first and second outputs of the register of channel identifiers are connected to the first one