SU826332A1 - Device for interfacing computer with telegraphic communication channels - Google Patents

Description

one

The invention relates to computing and can be used, for example, in automated control systems (ACS) for entering information from communication channels.

Devices for interface of a computer with channels are known, constructed using a long-term storage device (DSS), a switch of communication channels, a conversion unit for receiving received information, a distributor, a control unit, a start unit and a control panel J.

The disadvantage of these devices is the limited scope due to the maintenance of communication channels by a rigid program, which specifies a specific sequence and duration of service and does not allow an increase in the number of connected channels.

Closest to the proposed technical solution

is a device for connecting a computer to communication channels, containing a switching node connected by a first input and an output through a code converter with an output and input of a buffer memory, the address input of which is connected via an address switch to the outputs of the corresponding control registers and inputs of the poll distributor, the counter, nepBfaw and the second outputs connected to the corresponding 4 inputs of the code converter and the poll distributor, the outputs of which are connected to the first inputs of the And element, the first trigger and the registration control trench and a control input - with the output of the second flip-flop and a second input of the switching node 2J.

The disadvantage of this device is low bandwidth.

The purpose of the invention is to increase the capacity of the device. The goal is achieved in that the device containing the clock generator, the channel matching unit, whose inputs are the corresponding device inputs, the counter block, the information switch, the output connected to the information input of the memory block, the address switch and the matching block, with the computer , the output of which is the input-output of the device, a priority block, an address comparison block, an array of information analysis block and an OR element are entered, with a group of outputs for the end of message indication The channel matching unit is connected to the input-request group of the priority block, and the group of the formation outputs is connected to the informational inputs group of the information switchboard 20, the group of interrogative inputs of which is connected to the interrogation input group, the address switch, counting input group of the counter block, a group of inputs of the element OR and gdSD1Poy information outputs of the priority block, synchronizing the input and output of which are connected respectively to the output of the clock generator and the synchronizing input of the matching unit with the computer, whose information input is connected to the output of the package unit, the output of the read signal to the read input of the memory unit and the control input of the address switch and the address comparison unit, the output of the current address code to the information M inputs of the address selector and comparison unit addresses, and inputs of the code of the word, state and interruption request, respectively, to the first and second outputs of the block of analysis of the array of information, the group of inputs of which is connected to the group of outputs of the block of counters and groups of information inputs the address comparison unit and the address switch, the output of the OR element connected to the input, the output of which is connected to the write input of the memory unit, the output group of the connection address comparison unit with the reset input group of the counter unit. And by the fact that the angles block of the information array contains a group of encryption nodes of the array state, the inputs of which are connected to the corresponding inputs from the group of inputs of the block, the first outputs are connected to the first output of the block, and

the array states consisting of AND-NOT elements 24-27, the fifth element OR 28, the pulse shaper 29, the first - the fourth elements, the second outputs are connected to the corresponding inputs of the OR element, the output of which is the second output of the block, And also that the array state encryption node contains two triggers, the outputs of which are connected to the first output of the node, and the first and second inputs, respectively, to the outputs of the first - fourth elements OR, and the circuit of the NAND element, the outputs of which are connected to the corresponding bit buses of the inputthe node, the output of the first AND-NOT element is connected to the first inputs of the second, fourth and fifth OR elements, the output of the second AND-NOT element is connected to the second inputs of the second and fifth OR elements and to the first input of the third OR element, the second input of which is connected to the output of the first element AND-NOT, the first input of the first and third input of the fifth element OR, the fourth input connected to the output of the third element AND-NOT and the second input of the first and fourth elements OR, and the output through the driver of the pulses to the second output of the node. FIG. 1 is a block diagram. devices; in fig. 2 - functional block diagram analysis of the array of information. The device contains (Fig. 1) block 1 matching with communication channels, outputs 2 signals The end of the message of telegraph packages and information outputs 3 symbols of telegraph packages of block 1, generator 4 clock pulses., Block 5 priority, output 6 clock pulses of block 5, block 7 counters messages, address comparison block 8, information array analysis block 9, information switch 10, OR element 11, address switch 12. . , memory block 13, information input 14 and input 15, write signal input 16, read signal input 17 and address input 18 of block 13, current address code bus 19, current word code information bus 20, interrupt request signal bus 2i, block 22 matching with a computer (DVM). Block 9 analysis of the array of information includes (Fig. 2) nodes 23 encryption

OR 30-33 and triggers 34, and the element OR 35.

The device works as follows.

The current telegraph parcels of information coming from the communication channels to the inputs of block 1 are converted from a serial code into a parallel code for each telegraph link.

The block I of the formation of the parallel information code generates signals for the request inputs of block 5, the end of the message, and for the information inputs of the switch 10, the parallel code of the received message with the sign of the communication channel number.

At the outputs of block 5, according to the start priority, single pulses are received at the counting inputs of block 7 of message counters of each direction, the inputs of the OR 11 element, the interrogation inputs of switches 10 and 12, and the information inputs contain a specific address code with the channel number indication older bits. As a result, the incoming information is recorded in a certain area of block 13. As the array of information accumulates in block 13, block 9 generates a code for the word of the state of the array of each direction and, via bus 2, issues an interrupt request signal to block 22.

The digital computer, via block 22, processes the interruption request and, having received the status word code via information pin 20, can count the accumulated array of information distributed over different areas of block 13. For this purpose, block 22 exposes to input 17 and inputs of switch 12 and block 8 control signal, and bus 19 is the current address of the word to be counted from block 13. If the current address on bus 19 coincides with the address at the outputs of block 7, block 8 outputs the reset signals to the initial state of only those message counters whose readings match the current address with ityvaemogo array of information.

Let, for example, telegraphic parcels arrive in the form of a five-element code (start, five bits of information, stop) from receiving telegraph channels of communication. Block 22 communicates simultaneously with 8 channels and, as information is converted, produces an eight-bit information code for each of the channels, where the state of the older three bits indicates the code of the channel number. Block 13 of the memory in this example is a. Physical memory device (MOZU) for 4096 bytes of information. In this case, each channel will have the same MOZU memory areas equal to 512 bytes. The counting depth of block 7 of message counters is equal to the capacity of one memory area of the SHZU, t, e. is nine-bit counters.

The most significant bits of each message counter are assigned the same communication channel number flashed into the higher bits of the address switch, so that the address switch 12 has 12 data information inputs. Therefore, the information arrays arriving in directions accumulate in the memory areas of the MOZU defined for each direction, for example, a channel with a sign in the higher bits 000 - the memory area from the -th cell to 512, from the characters 001 - the memory area from 513 1024 cells, etc., i.e. each successive word of information entering the MOZU is sequentially recorded only in its own memory area.

The state of each of the memory areas of the MOZU is assigned 2 bits, and for the example under consideration, block 9 forms a 16-radar array spacing

where 2р, 1р - 1st reception telegraph channel;

4p, 3p - 2nd reception telegraph

channel;

16p, 15p - 8th receiving telegraph channel.

Each state corresponds to a definite sense code.

00 - No information - no information;

Information No. 1 is the presence of information; Information 3/4

filling in any area of the memory by 75%;

Information 1 complete filling of any of the memory areas.

The unit 22, when processing the digital computer, interposes the control input of the switch 12, the output 17 and the block 8, the control signal, and the information inputs of the Jmutator 12 and block 8-12, the discharge code of the current address on the bus 19,

During the transitions from 000 to i П in the leading digits of the current address of the readable information arrays, block 8 generates eight reset signals to the initial state, respectively, of 8 message counters of block 7, which allows accumulating new arrays of information that come in through 8 mi laziness m, Vlok. The analysis of the array of information forwards four states of the array. - The input of the element of the IS-NOT node 23, for example, for the first channel (FIG. 2) is connected to the zero outputs of the bits of the counter of the block 7 corresponding to the first channel, the inputs of the element AND NOT 26 to the single outputs of all bits of the same counter . Therefore, the signal at the output of the element AND-24 does not correspond to the state of the Information, but the element, AND-27 does not correspond to the state of Information 1. The output signals of the elements NO-25 and 26 indicate the state of the Information is - to the information 3/4 5 for which the inputs of the AND-NE element 25 are connected to the unit output of the first bit and the zero outputs of the remaining bits of the counter of the first channel a, j, and the inputs of the AND-NE element 26 to the unit outputs of the eighth and ninth bits and zero outputs of the others. counter bits. Thus, the device allows the simultaneous reception of information from a group of channels of channels, thereby providing an increase in production capacity. The formula of the invention is a device for interfacing a computer machine with telegraph communication channels, comprising a generator of sync1 O-pulses, a channel matching unit whose inputs are jj corresponding and device inputs, a block of counters, an information switch, an output connected to an information input of the memory block, an address commutator and a matching unit with the computer, the input-output of which is the input-output of the device, characterized in that, in order to increase the capacity of the device, it The priority block, the address comparison block, the block of analysis of the information array and the OR element are defined, with the output group of the sign of the end of the message of the matching block with the channels connected to the input group of the request for the priority block, and the information output group to the information input group of the information switch, a group of polling inputs which is connected with the group of polling inputs of the address switch, the group of counting inputs of the counter block, the group of inputs of the element I.GI and the group of information outputs of the priority block, synchronizing The input and output of which are connected respectively to the output of the clock generator and the synchronization input of the matching unit with the computer, the information input of which is connected to the output of the memory unit, the output of the read signal to the read input of the memory unit and the control inputs of the address switch and address comparison unit , the output of the code of the current address to the information inputs of the address switch and the address comparison unit, and the inputs of the code of the status word and the interrupt request respectively to the first and second outputs of the block analysis of the array of information, the input group of which is connected to the output group of the counter block and the information input groups of the address comparison unit and the address switch, the output of the OR element connected to the input, the output of which is connected to the recording input of the memory unit, the output comparison address group of the input unit reset block counters. 2. The device according to p., Characterized in that the block of an array of information contains a group of encryption nodes of the array state, the inputs of which are connected to the corresponding inputs from the group of inputs of the block, the first outputs are connected to the first one. the output of the block, and the second outputs are connected to the corresponding inputs of the OR element, the output of which is the second output of the block. 3. The device according to PP. 1 and 2, characterized in that the node

Encrypting the state of the array contains two triggers, the outputs of which are connected to the first output of the node, and the first and second inputs, respectively, to the outputs of the first to fourth OR elements, and four AND-NOT elements, the outputs of which are connected to the corresponding bit buses of the node input, the output of the first element AND-NOT is connected to the first inputs of the second, fourth and fifth OR elements, the output of the second AND-NOT element is connected to the second inputs of the second and fifth OR elements and to the first input of the third OR element, the second input of which is connected to move the fourth element

NAND, the first input of the first and the third input of the fifth element OR, a quarter input connected to the output of the third element NAND and the second inputs of the first and fourth element OR, and the output through the pulse shaper to the second output of the node.

Sources of information taken into account in the examination

1. Authors certificate of the USSR 433482, cl. G 06 F 3/04, 1972.

2, USSR Copyright Certificate No. 2623553 / 19-24,

cl. G 06 F 3/04, 1978 (prototype).

7 /

7p

2

Claims (3)

Claim I =. A device for interfacing a computer with telegraph communication channels, comprising a clock generator, a channel matching unit, the inputs of which are ₅₅ corresponding device inputs, a counter unit, an information switch connected to an information input of a memory unit, an address switch and a matching unit with a computer, the input-output of which is the input-output of the device, characterized in that, _5, in order to increase the throughput of the device, a priority block is entered into it, bl ok address comparison, an information array analysis unit and an OR element, the output group at ~ 10 signs of the message end of the matching unit with channels connected to the request input group of the priority unit, and the information output group to the information input group of the information switch, the polling input troupe of which connected to a survey group. the address switch inputs, the group of counting inputs of the counter block, the group of inputs of the OR element, and the group of information outputs of the priority block, the synchronizing input and output of which are connected respectively to the output of the clock generator and the synchronizing input of the matching unit with a computer, the information input of which is connected to the output of the memory block , read signal output - to the read input of the memory unit and the control inputs of the address switch and the address comparison unit, the current address code output to the information the input inputs of the address switch and the address comparison unit, and the status word and interrupt request code inputs, respectively, to the first and second outputs of the information array analysis unit, the input group of which is connected to the group of outputs of the counter unit and the information input groups of the address comparison unit and the address switch, the output of the OR element connected to the input, the output of which is connected to the recording input of the memory unit, the group of outputs of the address comparison unit is connected to the group of reset inputs of the counter unit. 2. The device according to π. 1, characterized in that the analysis unit of the information array contains a group of encryption nodes of the state of the array, the inputs of which are connected to the corresponding inputs from the group of inputs of the block, the first outputs are connected to the first. the output of the block, and the second outputs are connected to the corresponding inputs of the OR element, the output of which is the second output of the block. 3. The device according to paragraphs. 1 and 2, characterized in that the node encrypting the state of the array contains two triggers, the outputs of which are connected to the first output of the node, and the first and second inputs, respectively 826332 y AND-NOT, the first input of the first and third input of the fifth OR element, the fourth input connected to the output of the third AND-NOT element and the second with the outputs of the first-fourth OR elements, and the four AND-NOT elements whose outputs are connected to the corresponding bit input buses node, the output of the first AND-NOT element is connected to the first inputs of the second, fourth and fifth OR elements, the output of the second AND-NOT element is connected to the second inputs of the second and fifth OR elements and to the first input of the third OR element, the second input of which is connected to the output of tvertogo ring element inputs of the first and fourth OR elements, and output through the pulse shaper - to the second output uzla._