SU1282142A1 - Multichannel interface - Google Patents

Description

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The invention relates to computing and can be used in systems for processing multi-channel information entering a computer complex (VC) from remote groups of sources that are not synchronized with each other.

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The purpose of the invention is to increase the coefficient 128

equipment usage

The drawing shows a block diagram of the device.

The device contains channels 1,. switch group 2. Each channel contains a generator of 3 pulses, counters 4-6, elements and 7 and 8, registers 9 and 10, switches 11-14, a group of shift registers 15, trigger 16, decoder 17, node OR 18, node of elements AND 19, memory 20, delay element 21, AND group 22, encoder 23, trigger group 24, adder 25, matching nodes 26-29, group of output switches 30, group of input switches 31.

. The device works as follows.

Each group of information sources is served by its channel 1 and is synchronized by its pulse generator located along with the source of information.

In the operation of each channel of the device, two main modes of operation should be distinguished - work and control.

 In the operating mode, information signals in the form of a multichannel digital stream from an information source group are fed to the information input of their channel 1 and through the node 26 arrive at the input of the switch 11. In this mode, the switch 11 passes these signals to the input of the node of the OR elements 18. At the other input of the node OR 18 enters through the node elements AND 19 code of the current frame number from the output of the counter 5.

The code of the current frame number is generated by the counter 5 by counting the frame sync pulses received through the node 27 and the switch 12.

Enter the code of the current frame number

55 information is carried out into the information flow through node 28 and switch by node 18 at the moment of arrival of the delayed personnel pulse from the delay element 21, the delay in which is half the period

The torus 13. Resetting the counter 6 is performed by a frame sync pulse from the output of the switch 12. The read signs from the output and the memory 20 are transmitted

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clock sync pulses. The information flow thus generated from the output of the node of the elements OR 18 flows through a group of output switches 30 and one or several switches 2 into one or more VK computers. Together with each sample of information flow, a test bit is inserted into a computer through a group of output switches 30 and switches 2, which is calculated by adder 25 by adding up to odd evenness the sum of bits of information samples transmitted. In addition, together with the information flow through the group of output switches 30 and switches 2 computers 12 output clock sync pulses accompanying each frame of information, and from the outputs of one or more elements And 22 - clock sync pulses accompanying each information sample inside the frame . The connection of the information flow to one or several computers is controlled by the computers themselves, issuing addresses of the connected inputs of the switches 2 to the control inputs of the device.

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The device has the ability to be initiated by one or several

computing machines produce

in each channel 1, the selective synchronization of only a part of the information entered into the VC. For this, in each channel 1, counter 6 is used.

channels, memory 20 and group of elements 22. The control information containing the addresses of the channels and signs of their information transfers comes from computers through the group

the input switches 31 and the switch 14 in the memory 20. Prc. entering information into the computers reads the signs of the transmission of the channels from the memory 20 to the addresses,

coming from the output of the counter 6 channels. Counter 6 forms the address code from clock sync pulses coming into each channel from the source group of the introm 13. Counter 10 is reset by the frame sync pulse from the switch 12 output. Signs of the transfer read from memory 20

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are applied to the elements of AND 22 clock sync pulses and through a group of output switches 30 and switches 2 are inserted into computers.

At any one time, only one computer can load each channel with control information. At the same time, the computing machine exposes the activity sign in one of the bits of its control word supplied to the channel through the corresponding trigger 24, and the encoder 23 forms the address where the switch 14 connects the control input to its output. The control word from the output of the switch 14 is distributed between the register 10, the memory 20, the shift registers 15 and the trigger 16. The control word through the register 9 and the matching node 29 enters the transmission line to control the transmission line by the VC.

The operation modes in each channel 1 are controlled by the state of the trigger 16, which is established by the computer through a group of input switches 31 and the switch 14. When the trigger 16 is switched from a state corresponding to the operating mode, the state is corresponding. control; mode, the signal from the output of the trigger 16 turns off the switches in switches 11-13, inputs through which nodes 26-28 channel is connected to the source of information. From this point on, the second inputs of the switches 12 and 13 receive personnel and clock

Claims (1)

sync pulses generated to generate a payload of such a VC, a pulse generator of 3 pulses (. tact sync pulses) and a frequency divider, the formula of the invention, built on counter 4 and element I 7 (personnel sync pulses), 50 arrive at the second inputs of the switch 11 control information signals from the outputs of the group of registers 15 shift, the number of which is equal to the number of bits of the information code. The control of the shift registers 15 in the control mode is carried out by the pulses of the 3 impulses arriving at their inputs from the generator output through the AND 8 element with the Multichannel interface device, containing in each channel the first counter, the output of which is connected to the first memory input, the element delays, the output of which through the node of elements AND is connected to the input of node 5f of elements OR, adder, second and third counters, trigger, first and second registers, first switch, first and second elements AND, group of elements AND, o duplicating O the rank of the enable signal from the trigger output 16. The structure of the information flow in the control mode is specified by the computer by pre-recording the specified code combinations into each of the shift registers 15. The writing to the indicated registers is carried out by means of special control words containing the write code and the register address and arriving respectively at the write inputs of the shift registers 15 and the input of the register 10. The write control is maintained. 5 m signals decoder 17, connected by its input to the output of the register 10, Thus, the introduction of additional units into a multichannel device for interfacing allows for the automatic reconfiguration of information and control flows, as well as monitoring its operation. 5 by means of a software-controlled simulation of the transmitted digital stream. This will allow a substantial improvement in the performance of the input system (such as survivability 0 and the testability of the system, the reliability of the transmitted information). As a result, the equipment utilization ratio will increase due to the decrease in the number of possible simple 5 s of the computer complex arising due to failures of a part of the device channels for interfacing or channels of computers. Compared with the known device, the use of the proposed device in conjunction with the VC, built on the basis of the PS-2000 expeditionary geophysical computing complexes, will increase the payload of such a VC by 8-10%. A multichannel interface device, containing in each channel the first counter, the output of which is connected to the first memory input, a delay element, the output of which through the node of elements AND is connected to the input of the node of elements OR, adder, second and third counters, trigger, first and the second registers, the first switch, the first and second elements AND, the group of elements AND different In order to increase the equipment utilization ratio, two to four commutators, a decoder, an encoder, a group of shift registers, a trigger group, an input switch group, a group of output switches, each generator output connected to the first input of the first commuting input, are entered into each channel switchboards of groups, the first and second outputs of which are connected respectively to the inputs of the fourth switchboard and group triggers, the outputs of which through the encoder are connected to the input of the fourth switchboard and whose output is connected to the second input of the memory inputs of the first and second registers. tator, the inputs of the first, second ele-Yu trigger and the second inputs of registers And the second counter, the output of which through the first AND element is connected to the first input of the second switch, the output of the first register through the decoder is connected to the first inputs of the group shift registers, the outputs of which are connected to the first input of the third switch, the output of which through the node of the elements OR is connected to the first inputs of the output switches of the 20 th and third switches, the output the group and the input of the adder, the output of which is connected to the second inputs of the incoming switchboards of the group, the memory outputs through the corresponding AND elements of the group are connected to the third inputs of the output switches of the group, the outputs of which are connected to the group of outputs of the channel, the group of inputs of which are connected to the inputs of the corresponding input switchboards of groups, the first and second outputs of which are connected respectively to the inputs of the fourth switchboard and group triggers, the outputs of which through the encoder are connected to the input of the fourth switchboard pa, whose output is connected to the second input of the memory inputs of the first and second registers. trigger and second register inputs shift group, the trigger output is connected to the second inputs of the first, second and third switches and through the second element I to the third inputs of the group shift registers, the output of the second register is connected to the channel output, the first, second and third inputs of which are connected to the third inputs of the first, second respectively the first switch is connected to the inputs of the elements And group and with the first input of the first counters, the output of the second switch connected to the second input of the first counter, with the fourth inputs of the output switches of the group, the input of the delay element and through the third counter with the input of the node elements I.