SU1456956A1 - Multichannel device for controlling the servicing of requests in the order of arrival - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to control the queue-hoctbro service of subscribers in the order of receipt of their requests. The aim of the invention is to increase speed. The device contains an OR 10 element, an AND 11 element, a delay element 12, an OR-NOT 13 element, counters 15 and 16, a service end sensor 14 and channels 1 including triggers 2,3,5,9, elements 4 and 8, a cell memory 6 and comparison circuit 7. When multiple requests for device inputs are received at the same time, the queue number is recorded from counter 15 in memory cell 6 of that channel, whose priority for writing to the queue is higher. The delay in writing to the queue and the provision of service in the absence of a queue are determined by the switching times of the channel elements and do not depend on the number of channels in the device. The processes of writing to the queue and providing services in accordance with the queue number received go independently of each other. I il. § (L

Description

The invention relates to computer technology and for controlling the subscription of their requests.

The purpose of the invention is to increase the speed of the device.

The drawing shows a structural diagram of the device.

The device contains channels 1, in each canap triggers 2 and 3, element And 4, trigger 5, memory cell 6, a comparison circuit 7, element And 8 and trigger 9, the device also contains ele * · 15 ment OR 10, element And 11 , delay element 12, element OR NOT 13, end-of-service sensor 14, counters 15 and 16, device outputs 17 and device request inputs 18.

The device operates as follows.

Before starting the service, the counters 15 and 16 are set to the same state, for example, in ’’ O, and the high-order bits of memory cells 6 and triggers 2 and 9 are reset. At the inputs of the last category of memory cells 6 and the last category of the second group of inputs of comparison circuits 7, a logical 1 signal is installed,

Upon receipt simultaneously of the inputs 18 of two service requests in the form of a logical signal ⁿ 1 ". the corresponding triggers 2 switch along the edge to state 1, Sig ·? ' Slots 1 from the outputs of these triggers go to the inputs of the OR element 10, from the output of which the signal goes to the first input of the And 11 element, at the second input of which 'установлена is set at this time, since the triggers 5 of all channels are in state 0, C of the output And element 11, signal 1 goes to the clock input of triggers 3 channels and switches triggers 3 to state “1, so as a logic 1 signal at their inputs set to” 0 allows them to synchronize (work, Signals 1 from direct outputs of triggers 3 go respectively inputs of elements AND 4. Signal ”0 s inverted trigger 3 output goes to the elements And 4 subsequent channels.

Thus, at the inputs of all elements And 4, except for one, a signal 0 is generated that holds the corresponding triggers 5 in state 0. From the output of the delay element 12, signal 1 is fed to the clock inputs of all triggers 5 and switches the corresponding trigger 5 to 1, Forward the front of the signal e of the output of trigger 5 in the corresponding cell 6 enters the contents of the counter 15 (in this case, all 0), in addition, the signal from the output of trigger 5 through the element OR-NOT 13 closes the element And 11. In the last bit of the cell 6 is entered 1, Unit since the last exit Key 6 sets the corresponding trigger 2 to 0, it sets the zero signal from the output of trigger 2. corresponding trigger Zi trigger 5 are poured into "0". At the same time, 1 appears on the output of the OR-NOT 13 element, which adds l "to the contents of counter 15, Then the process repeats as described above and, if until the second trigger 2 is switched to 0, none requests are not received from the device’s inputs, the output of the AND AND element is 0, and the recording process in the queue stops.

After writing the code 00 ... 0 from the counter output to cell 6. 15 and logical 1 in the high order code 100 ,,, 0 goes to the first inputs of the corresponding comparison circuit 7, to the * second inputs of which the code 00.,. 0 comes from counter 16 and 1 to the high order. At the same time, a high logic level is formed at the output of the comparison circuit 7, which is fed to the first input of the corresponding element And 8, at the second input of which there is 1 from the sensor 14, since there was no maintenance before. Therefore, at the output of element And 8, 1 is formed, which switches the corresponding trigger 9 to state 1, Signal 1 from the output of trigger 9 goes to the corresponding output of the device 17, At the same time, the signal from the output of trigger 9 arriving at the input of the unit at 0, cell. 6 is reset and the current signal 1 is removed from the installation input to 0 of trigger 2,

The signal 0 is generated at the output of the comparison circuit 7, as a result of which the signal 0 is also generated55 at the output of the And 8 element. At the beginning of the service, the logical 1 signal is removed from the output of the sensor 14 of the end of the service, and the counter 16 switches to

1456956 melt 00. ,, 01, and trigger 9 is reset,

In this case, on the channel comparison circuit 7, the first input of which receives the code 100 ,,. 01 from the output of the memory cell 6, a match is obtained, and from its output, the signal 1 arrives at the first input of the And 8 element.

At the end of servicing the device connected to input 18, 1 is formed again at the output of the sensor 14 of the end of service, and the signal from the output of element And 8 switches to 1 trigger 9, The device connected to input 18 receives permission and proceeds to service. In this case, the formed front of the signal from the output of the sensor 14, the counter 16 switches to the state 00 ,,. 10,

If during the service of this device a request appears on the other inputs of the device, then their service will occur in the same order in which they arrived, and when several requests are received simultaneously, they are written into the queue and served in ascending order of the number of channels.

Claims (1)

Claim A multi-channel device for managing the service of applications in the order of receipt containing the element. OR, delay element, first and second counters, end-of-service sensor, and in each canap, first and second AND elements, first trigger, memory cell and comparison circuit, and <in each channel, the information inputs of the memory cell, except for the last input, are connected to the outputs the first counter, the group of outputs of the channel memory cell is connected to the first group of inputs of the circuit for comparing its channel, the second group of inputs of which, in addition to the last input, is connected to the outputs of the second counter, the counting input of which is connected to the output of the end serving the first inputs of the first elements AND channels, the second inputs of which are connected to the outputs of the circuit comparing their channels, the outputs of the first elements and channels are connected to the individual inputs of the first triggers of their channels, which differs in that, in order to improve performance, they are introduced into it element AND, element OR-HE, and in each channel the second, third and fourth triggers, moreover, in each reset channel of the second trigger is connected by the output of the second element And, the reset input of the first trigger is connected to the output of the sensor end of service I, the output of the first trigger of each channel is the corresponding output of the device and is connected to the installation input in 0 memory cells of its channel, the output of the last bit of which is connected to the reset input of the third trigger of this channel, the clock input of the third trigger of each channel is the corresponding request input of the device, the output of the third the channel trigger is connected to the input from the reset of the fourth trigger, the input of the OR element, the output of which is connected to the first input of the AND element, the second input of which is connected to the output of the element and OR-HE and with the counting input of the first counter, the output of the AND element is connected to the clock inputs of the fourth channel triggers and the input of the delay element, the output of which is connected to the clock input of the second channel triggers, the outputs of which are connected to the recording memory control inputs of the channels and the input OR-HE element, the information inputs of the second, third and fourth channel triggers are connected to the input of the logical unit of the device, the last information inputs of all memory cells are connected to the input of the logical unit of the device, last the first inputs of the second groups of inputs of the channel comparison circuits are connected to the input of the logical unit of the device, the direct output of the fourth trigger of each channel is connected to the first input of the second element * of its channel, the inverse output of the fourth trigger of each channel is connected to the corresponding input of the second element And of each next channel,