SU1411744A1 - Priority device - Google Patents

Description

keys to the output of the third element OR and to the installation input of the counter, the installation input of the request register is connected to the output of the first block of elements OR, the information input of the second decoder is connected to the output of the counter, the service end input of the device is connected to the second input of the fourth end OR, whose output is connected to the installation the input of the current priority register, whose information input is connected to the output of the second block of OR elements, the first input of which is connected, to the output of the block of AND elements and to the information The device’s input / output, and the second input of the second block of elements OR are connected to the first input of the block of Inc elements, the output of the memory block, the reset input of the device is connected to the second input of the third element OR, the input Read of the memory block is connected to the output of the first element OR, the write input the device address is connected to the gate input of the counter, the device’s read input is connected to the second input of the I block, and the device’s write input to the Record input of the memory block.

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The invention relates to computing, in particular, to devices for priority service of requests, and can be used in an information exchange system. five

The purpose of the invention is to expand the functionality of the device by servicing the request signals of both potential and pulse types. ,ten

The drawing shows a block diagram of the device.

The device contains information input / output 1, address input 2, output 3 chipping, memory block 4, counter 5, current priority register 6, request switch 7, decoder 8, AND 9 element, comparison circuit 10, request trigger 11, element 12, query register 13, element 20 OR 14 / blocks 15 and 16 elements OR, elements OR 17 and 18, decoder 19, service end input 20, clock input 21, group of query inputs 22, reset input 23, input 24 initial settings, entry 25 entries; priority, write input 26, read input 27, address write input 28, AND block 29 and OR 30 block.

The priority device works in the 9th way.

Information about all services is preliminarily recorded in block 4 of memory. subscribers: masking request, subscriber priority, type of request. 35 Recording occurs as follows.

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9

five

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The signal containing the subscriber information, via the information input / output 1 of the device, enters the information input of the memory 4. The signal containing the cell address of the memory block 4 through the address input 2 of the device enters the information input of the counter 5. The signal from the input 28 of the recording of the address of the device 28 enters the gate input of the counter 5. Thus, the output of the counter 5 carries the signal from the address input 2 of the device, which arrives at the address input of the memory block 4.

The signal from the device record input 26 is input to the record of memory block 4. Thus, the cell of memory block 4, whose address is determined by the signal at device address input 2, records information from the device information input / output 1. Writing to other cells of memory block 4 is similar. Each cell of memory block 4 corresponds to one serving subscriber, with the first cell corresponding to one serving subscriber, the first cell corresponding to the subscriber having the highest priority, and the last to the subscriber having the lowest priority. The information in memory block 4 may be further modified during operation of the device.

After the subscriber information has been entered into the memory block 4, the priority device is transferred to the initial state, i.e. the signal from the input 24 of the initial installation of the device simultaneously arrives at the inputs of the element OR 14, the block 15 of the elements OR, and the element OR 17. The active signal from the output of the element OR 14 is fed simultaneously to the installation inputs of the trigger P request and counter 5 ,. which brings them back to their original state, i.e. at the output of the counter 5, the cell address of the memory block 4 is set, c. where the information about the subscriber having the highest priority is recorded, and a signal is set at the output of the request trigger 11.

meaning for the service device-20, to the other input of which the message arrives that there is no interruption. The active signal from the output of the block 15 elements OR is fed to the installation input of the register 13 requests, which leads to its reset. The active signal from the output of the element OR 17 goes to the setup input of the register 6 of the current priority, which leads to the installation on its vpsode signal corresponding to the lowest priority register 6 of the current priority, then

that

Until at least one request for termination coming from the group of request inputs 22 of the device to the gate input of register 13 of requests is prioritized, the priority device is in the request waiting mode, since the inhibit signal from the output of register 13 of requests is simultaneously received at the second input of the AND element 12 and the input element OR 30 that. prevents the appearance of active signals on their codes, which are connected respectively to the counting input

counter 5 and input Read unit 4 dd ° gate input trigger 1I

memory

When appearing from the group of interrogation inputs 22, the interrogation request device from the subscriber at the output of the query register 13 appears the active signal, which simultaneously enters the input of the AND 12 element, the input of the OR 30 element, and the information input of the request switch 7. The input element And 12 from the clock input 21 of the device receives a constant signal with a certain frequency. These signals from the output of the element I I2 arrive at the counting input of the counter 5.

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with (Q | 5

5 starts working in counting mode. The active signal from the output of the element OR 38, arriving at the input Reading block 4 of memory, puts it into read mode.

Since the output of the counter 5 is connected to the address input of the memory 4, a sequential polling of all the cells of the memory 4 occurs, and the polling starts from the cell in which information about the subscriber with the highest priority is recorded. The output of counter 5 is also connected to the address input of the request switch 7 and to the information input of the decoder 19. The signal from the output of memory block 4 is simultaneously fed to the input of the decoder 8, to the input of the comparison circuit 10,

from the output of register 6 of the current priority. The comparison circuit 10 compares the priority recorded in the register of the current priority register 6 with the priorities recorded in the memory block 4.

If the IO comparison scheme reveals that the subscriber’s priority is higher than or equal to the priority recorded

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from the output of the comparison circuit 10, the active signal is fed to the input of the AND 9 element. If the decoder .8 detects a non-masked request of the required type, then an active signal comes from its output to the input of the And 9 element. If the request switch 7 detects a request from the subscriber, then an active signal comes from its output to the input of the And 9 element.

If there are simultaneously three active signals at the inputs of the And 9 element, its output is the active signal, which arrives simultaneously

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request, the input element OR 18 and the gate input of the decoder 19, which causes the request trigger 11 to be thrown, active signals are output on the OR 18 and the decoder 19 outputs. The request trigger signal 11 is output from the request trigger 11 output to the output 3 of the interrupt devices. At the same time, this signal arrives at the inputs of the AND 12 and OR 30 elements. This leads to the cessation of the passage of signals from the clock input 21 of the device to the output of the AND 12 element, which leads to the end of the counting mode | of the counter 5.

j The active signal at the input of the element OR 30 continues to maintain the active signal at its output, which prolongs the reading mode of memory block 4. The active signal from the output of the decoder 19 is fed to the input of the block 15 of I-UM elements, which leads to an active signal at its output, which is fed to the installation entry register of the query 13. A drop is exactly the request for which the interrupt signal is sent to the service device. The active signal from the output of the element OR 18 is fed to: the tamping input of the register 6 of the current priority, which leads to the record: and into this priority register from the output of memory block 4 through the block of 16 OR elements.

When the servicing device receives the signal of the pregloan, it, on the way of the device shadow 27, generates a 1K signal, which is fed to the input of the block 29 of the elements AND, which translates the information about the output of the memory 4 to the information input / output 1. of the device. Thus, the server will read from the priority device the type and priority of the subscriber. Then, the servicing device, at the input of the device, inserts the active signal, which resets the trigger P of the request and the counter 5, thereby preparing the priority device for further operation.

After the termination of the service of the 1-1vnta servicing device along the 20th end of the servicing of the device, the ifcTBa activates the active signal arriving at the input of the element OR 17, and. The active signal at its output sets the current priority register 6 to the initial state, i.e. enters the signal corresponding to the lowest priority.

If, during the service of a subscriber, a request from a subscriber with a lower priority appears, the priority device does not receive a stop signal on exit 3, since from the output of the comparison circuit JO, the inhibit signal and request trigger J1 come from the output of the comparison circuit JO. Do not transfer.

If during the service of any subscriber a request from a subscriber with a higher priority appears, the priority device triggers the interrupt signal according to the described principle. Subscriber service with more

The low priority is terminated and service to the subscriber with a higher priority begins. After the end of the service of this subscriber, the service device sets

on the information input / output 1 of the device information corresponding to the Priority of the subscriber whose service was interrupted. This information is fed to the input of block 16 of the OR elements and is transferred to its output, which is connected to the information input of register 6 of the current priority. Next, the server sets the active signal to

input 25 records the priority of the device, which is fed to the input of the element OR 18, from the output of which the active signal goes to the strobe input of the register 6 of the current priority,

which leads to the recording of the priority of the subscriber whose service is interrupted. Further, the service of this subscriber continues.

Upon the arrival of the next unasked request from the subscriber, the sequence of all operations is repeated.

Claims (1)

A PRIORITY DEVICE comprising a memory block, a counter, a current priority register, a request switcher, a first decoder, a comparison circuit, a first AND element and a request trigger, the information input / output of the device is connected to the information input of the memory block, the output of which is connected to the input of the first decoder and the first input of the comparison circuit, the second input of which is connected to the output of the current priority register, and the output Greater than or equal to the comparison circuit is connected to the first input of the first AND element, the output of which is connected to the strobe the input of the trigger for recording the request, the output of which is the output of the device’s conversion, the second input of the first element And is connected to the output of the query switch, the control input of which is connected to the output of the counter and to the address input of the memory block, the information input of which is the information input of the device, the output of the first decoder is connected to the third input of the first element And, characterized in that, in order to expand functionality by servicing request signals of both potential and pulse type, the second AND element is entered into it, the request register, the second decoder, the first, second, third and fourth OR elements, the first and second blocks of OR elements, the block of AND elements, and the group of request inputs of the device is connected to the group of gate inputs of the request register, whose signal output is connected to the first input of the second AND element, and the information output is to the first input of the first OR element and to the information · input of the query switch, the counting input of the counter is connected to the output of the second And element, the second the third inputs of which are connected respectively to the clock input of the device, to the second input of the first OR element and to the output of the request trigger, the input of the device priority record is connected to the first input of the second OR element, the output of which is connected to the gate input of the current priority register, and the second input of the second OR element connected to the gate input of the second decoder and to the output of the first AND element, the output of the second decoder is connected to the first input of the first block of OR elements, the second input of which is connected to the first the input inputs of the third OR element, the fourth OR element and to the input of the initial installation of the device, the installation input of the request trigger under-_ .. keys to the output of the third OR element and to the installation input of the counter, the installation input of the request register is connected to the output of the first block of OR elements, information the input of the second decoder is connected to the output of the counter, the input of the end of service of the device is connected to the second input of the fourth OR element, the output of which is connected to the installation input of the current priority register, information ny input of which is connected to the output of the second OR element unit having a first input connected. to the output of the block of AND elements and to the information input / output of the device, and the second input of the second block of OR elements is connected to the first input of the block of AND elements and to the output of the memory block, the reset input of the device is connected to the second input of the third OR element, input Read block the memory is connected to the output of the first OR element, the input record address of the device is connected to the strobe input of the counter, the read input of the device is connected to the second input of the block of ele- ments, AND, the input of the record of the device to the record input of the memory block. 1 .