SU1603393A2 - Device for controlling exchange between processor and memory - Google Patents

Abstract

The invention relates to computing and can be used to build systems with high-speed memory of large information capacity and is an improvement of the device along. N 1488816. The aim of the invention is to expand the field of application. The device contains the first, second counters of address 1, 2, trigger 3, generator 4 pulses, first, second memory blocks 5, 6, distributor 7 pulses, first, second blocks of elements And 8, 9, first through fourth elements And 10- 13, first, second blocks of elements OR 14, 15, first, second, third delay elements 16, 17, 18, first, second decoders 20, 21, format boundaries first, second groups of switches 22.23, element OR 26, counter 27 pulses, the third group of switches 28, the decoder 29 of the end of the parcel. The device provides a processor with two memory blocks with the formation of an interrupt upon completion of the exchange session. 1 il.

Description

The invention relates to computing, can be used to build systems with high-speed memory of large information capacity, and is additional to auth., No. 1A88816

The aim of the invention is to expand the scope of application by forming signals of the border of the image format of the information package and its end.

The drawing shows a block diagram of the device.

The device contains the first 1 and second 2 address counters, trigger 3, the generator of pulses, the first 5 and second 6 memory blocks, the distributor 7 pulses, the first 8 and second 9 blocks of elements And, the first 10, the second 11, the third 12 and the fourth 13 And elements, the first 14 and second 15 blocks of the OR elements, the first 16, the second 17 and the third 18 delay elements, the input 19 of the device for connecting the processor start output, the first 20 and second 2 decoders of the format boundaries, the first 22 and second 23 groups of switches, output 24 of the decoder 20, output 25 of the decoder 21, the element IGM 26, counters 27 pulses of the third group of switches 28, decoder 29 posshki completion.

The device works as follows.

The information recorded in memory blocks 5 and 6 is gated with a trigger signal input to input 19 and, if necessary, can be synchronized with recording frequency pulses from the output of generator 4. The trigger signal is also used for the initial installation of counters 1, 2 and 27.

The information to be recorded is set up at the information inputs of blocks 5 and 6, and the recording is made in parallel, for example bytes.

The single position of the trigger 3 corresponds to the write mode in the memory block 5 and the read mode for the memory block 6.

In the information recording mode, for example, in block 5, recording frequency pulses pass through delay element 16 and opened with trigger 3 evil0

five

0

five

0

five

0

ment And 10, also come to the element 17 of the delay.

The response time of the delay element 17 is shorter than the response time of the element 16, therefore the read-write inputs to the write frequency pulse arrive earlier in relation to the signal at the memory block sample inputs, which is a necessary requirement in the recording mode for blocks 5 and 6.

The end of the pulses for accessing the read-write and sampling inputs occurs simultaneously, because after the write pulse ends, the output of the delay element 16 is disconnected from the sample input using a closed AND 12 element controlled by the write frequency pulses, and the response time of the delay element 17 is equal to the trigger time of the elements And 12 and or 14 in the memory block sampling input circuit.

In read mode, information from memory blocks 5 and 6 is selected sequentially using distributor 7, which, through the appropriate blocks of elements AND 8 or 9, controlled by trigger 3, generates alternately accessing the sample inputs of memory blocks through the corresponding elements OR 14 or 15.

The address in blocks 5 and 6 of the memory is changed using the corresponding counter 1 or 2 on the last pulse, for example, the eighth, from the output of the distributor 7, which is fed to the input of counter 1 or 2 from the output of the corresponding element OR

14 or 15.

Using the switches 22 and 23, the inputs of the decoders 20 and 21 are used to set the codes of the expected sizes of the information format and, when the address code in the counters 1 and 2 coincides with the set code on. switches 22 and 23, decoders 20 and 21 deliver a format border pulse: the number of these pulses is counted by counter 27, switch 28 sets the code for the expected size of the pad and, when it coincides with the code of the counter 27, the output of the decoder 29 is generated at the output of the decoder 29, which ends the exchange process.

Claims (1)

Invention Formula A device for controlling the exchange of a processor with memory on auth.s. No. i4888 16, characterized in that, in order to expand the field of application, the element OR, the first, second form decoder form hectares, pulse counter, first, second, third group of switches and descriptor of the termination of the trigger, and the trigger output connected to the nth input of the first decoder of the format boundaries, the inverse output of the trigger is connected to the nth input of the second decoder of the format boundaries, the outputs of the first, second address counters are connected respectively to the first contacts of the switches of the first, second groups, sec whose contacts are connected to the bus of a unit potential of the device, 1 and (i 1 ,,,,, p-1) switch contacts of the first and second groups of switches are connected respectively to the i-th inputs of the first and second decoder format boundaries, the outputs of which are connected respectively with the first, second inputs of the element OR, the output of which is the same with the counting input of the counter pulses, the outputs of which are connected to the first contacts of the switches of the third group, the second contacts and the switching contacts of which are connected respectively to the unit potential bus and to the input of the send end decoder, the output of which is connected to the output of the device for connecting to the interrupt input of the processor, the reset input of the counter pulses are input devices for connecting to the processor start output.