SU1644148A1 - Buffer memory - Google Patents

Abstract

The invention relates to computing and can be used as a buffer memory for interfacing information flows in real-time devices. The purpose of the invention is to increase the speed of the device. In the device, switching occurs after reading all the recorded information in one of the memory blocks. To implement this method, triggers, AND –NE elements, inverters, and AND element with the appropriate connections are introduced into the device. 1 il.

Description

The invention relates to the field of digital computing, in particular, to buffer storage devices that allow efficient use of computers when entering information, and can be used in systems for processing information flows, as well as for building processor systems with fast memory.

The purpose of the invention is to increase the speed of the device.

In the device, the switching of the memory blocks occurs after all the information stored in the recording mode, i.e., is read from any memory block. switching occurs when the memory block in read mode is zeroed, and not when the memory block in write mode is full. A sign of zeroing the memory block is reading the last word jKa from it, which is written to the memory block just before the moment when the memory blocks are switched.

The drawing shows a diagram of the device.

The device contains two counters 1 and 2 addresses, two blocks 3 and 4 of memory, a generator of 5 pulses and a control circuit including 6-tO triggers, element 11, inverters 12 and 13, elements AND 14-16 and two switch 17 and 18.

The device works as follows.

In the absence of a Start signal, the counters 1 and 2 addresses are reset, triggers 7-9, trigger 6 are set to one. Low potential from the direct output of the trigger 9 enters the address input of the switch 17, as a result of which the write pulses arriving at the first and second inputs of the switch 17c of the generator 5,

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passes to the outputs of the switch 1 7 and is fed to the address counter 1, memory block 3 and trigger 6, i.e. the lowest potential at the forward output of the trigger 9 corresponds to the write mode in memory block 3, and the high potential from the inverse output of the trigger 9 arrives at the address input of the switch 18, which corresponds to the choice of the third input of the switch 18, which has a high potential, and the fourth input of the switch 18, to which read pulses are received from generator 5, which corresponds to the read mode from memory block 4. However, the high potential from the inverse output of the trigger 7 is fed to the control input of the switch 18 and prohibits the passage to the outputs of the switch 18 control signals from the third and fourth inputs. Therefore, reading from memory block 4 does not occur. This state of the device is initial to the arrival of the Start signal, i.e. the device is ready to record the incoming information in the memory block 3, since in the memory block 4 there is no information, it is

almost off

and reading from it does not occur.

After the arrival of the Start signal, the information to be written to the memory block 3 is associated with the Start signal and synchronized by the recording frequency P from the generator 5. The recording pulses from the output of the switch 17 enter the memory block simultaneously with the pulses of memory selection, thereby becoming it is possible to do without a complicated scheme for the formation of a timing diagram containing delay elements. The pulses of choice of memory block 3 at the same time are pulses of modification of the counter of address 1, the state change of which occurs on the falling edge of the pulse of selection of the memory block.

Thus, the information is recorded in memory block 3 before the arrival of the End of Word (CK) signal. The need for a CC signal is due to the fact that during a series-parallel transmission of information, each word must be initialized in order to avoid loss of information. In the event that the length of the transmitted word corresponds to the information width of the memory block, the CC signal accompany

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Each parcel of recorded information is given. Switching the memory blocks according to the CC signal avoids a situation in which a part of the recorded word is in one memory block and a part in another.

When a CS signal arrives at the device input, the trigger 8 is set to a high state, since a low level potential from the trigger output 7 arrives at the input of the NANDY element 14. in memory block 3 at the input D1.

On the back edge of the CS signal, the trigger 9 changes its state and at the forward output of the trigger 9 a high potential is established which arrives at the address input of the switch 17. As a result, the output of the switch 17 receives signals from the third and fourth inputs of the switch. The low potential from the inverted output of the trigger 9 goes to the address input of the switch 18, thereby making it possible for the signals from the first and second inputs of the switch 18 to pass to its outputs. This device state corresponds to the write mode in the memory block 4 and the read mode from the memory block 3.

The reset circuit, built on trigger 10 and elements 11,13 and 16, t generates a reset pulse tied to the read frequency, setting triggers 6 and 7 to a high state, tamping counter 1 and 2 and setting trigger 8 to a low state . The device switches to this initial position any time after switching the memory blocks.

The information to be written to the memory unit 4 is recorded in the same way as it was recorded in the memory unit 3. However, the termination of the recording occurs at the CC signal only when the information recorded in memory block 3 is fully read, as evidenced by the reading of the sign of the last recorded word from memory block 3 from the output D1. This happens as follows.

In the process of reading from the memory block 3, a high potential is fed to the write enable input of the block 3 from the switch 1 7, which holds the memory block in

read mode. The pulses of memory block selection, formed by the read frequency Fc, simultaneously arrive at the address counter 1 and the trigger 6, on which the presence of the sign of the last word recorded in block 3 is recorded. When the counter 1 reaches the address where the last word in block 3 is written, a low potential appears at the output D1 of block 3 - a sign of the last word that is fixed at the falling edge of the memory block selection pulse on trigger 6, the signal from the direct output of trigger 6 enters the element AND-NOT 14 and sets a high potential at the input D of the trigger 8, preparing the circuit for switching. The high potential from the inverted output of the trigger 6, which enters the control input of the switch 17, blocks the output of the memory block selection signals 3 and, therefore, the counter modification signals .1 of the address through the switch 17. With the arrival of the CC signal, the memory blocks works as described above.

The information read from memory blocks 3 and 4 can be combined into one channel using a switch controlled by trigger 9 or via OR elements, and synchronized by the read frequency.

Claims (1)

The invention includes a buffer memory containing two address counters, two memory blocks, a first trigger, a pulse generator and switches, the outputs of the first and second address counters are connected to the address inputs of the first and second memory blocks, respectively, the information inputs of the first and second address counters connected to the first and second outputs of the first and second switches, respectively, the second and first outputs of which are connected to the inputs of chip selection and recording resolution of the first and second blocks am ti respectively, a direct output of the first flip-flop connected to the first control input of the first switch, the inverse output of the first flip-flop connected to the first control input of the second switch, the first pulse generator output is connected with the first informational input of the switch, the second five the output of the pulses is connected to the second information inputs of the switches, the first and second information inputs of the memory blocks are respectively the first and second information inputs of the device, the first and second outputs of the memory blocks are information outputs of the device, with the second to the fifth, three IS-NOT elements, two inverters and an AND element whose output is connected to the outgoing inputs of the address counters and the fourth trigger and with by the second trigger input, the second and third trigger information inputs are connected to the second outputs of the memory blocks, the first and second inputs of the first NAND element are connected to the forward outputs of the second and third triggers, the inverse outputs of which are connected to the second control inputs of the first and second switches, respectively, the output of the first element AND is NOT connected to the information input of the fourth trigger, the synchronization input of which is connected to the input of the first inverter and the third output of the pulse generator, The output of the inverter is connected to the first input of the second NAND element, the second input of which is connected to the direct output of the fourth trigger, the inverse output of which is connected to the second information inputs of the memory blocks, the output of the second element AND NOT to the synchronization input of the first trigger and information input the fifth trigger, whose synchronization input and the input of the second inverter are combined and connected to the second output of the pulse generator, the inverse output of the fifth trigger and the output of the second inverter are connected respectively to ne The first and second inputs of the third NAND element, the output of which is connected to the installation input of the third trigger and the second input of the AND element, the first input of which is connected to the outlets of the first and third triggers, and is the device start input, the synchronization inputs of the second and third triggers connected to the first output of the first switch and the second output of the second switch, respectively. 0 five 0 five 0 five