SU1589285A1 - Device for interfacing source and receiver of information - Google Patents

Abstract

The invention relates to computing and can be used to exchange information in data acquisition and processing systems. The aim of the invention is to enhance the functionality by providing an operational change in the priority of the input information and excluding unnecessary information from the processing. The device contains two memory blocks, two multiplexers, a write address counter, a read address counter, a volume counter, a decoder, two delay elements, two single-vibrators, four AND elements, a group of AND elements, an OR element, and an NOT element. 1 il.

Description

The invention relates to computing and can be used to exchange information for data acquisition and processing systems.

The aim of the invention is to enhance the functionality by providing an operational change in the priority of the input information and excluding unnecessary information from the processing.

The drawing shows the block diagram of the device.

The device contains memory block 1 multiplexers 2, 3, memory block 4, delay element 5, one vibrator 6, elements AND 7-10, element 11, the counter 12 of the write address, counter 13 of the read address, element OR 14, the group of elements And 15, the element 16 delay, one-shot 17, the counter 18 volume, the decoder 19, the inputs and outputs 20-30,

The device works as follows

In the initial state, the counters 12, 18 and the memory elements of the memory block 4 are in the zero state, the counter 13 is in the single state. Before starting work in block 4 of the memory, ENTER with information on the basis of the co-. Secondly, the priority of the incoming information is determined in the following. Unit cell state in block

4 of the memory means the presence of priority information, the zero state of the cell means the absence of priority information. Input 28 is set. A high level signal is applied, switching memory block 4 to the recording mode, and the address input through multiplexer 2 connect input 27, Pulses are received at input 25, which according to addresses at input 27

ate

00

with

rsO 00 SP

20

In memory block 4, information is entered, the post is ada1a to input 29a. At the end of the augmentation, input 29 does not receive a low level signal, switching memory block 4 j in reading mode, and to the address input through multiplexer 2 connects information input 20, after which the device ready to work

Upon receipt of information at the Q input 20, accompanied by a pulse, at input 30, which does not require priority transmission, the signals at the first and second outputs of block 4 are high and open elements t5 And 7 and 8, Signal 30 at the input And 7 is fed to the control input of the multiplexer 3 and connects to the address inputs of the bit unit of the write address counter 12, then the signal from the output of the single vibrator 6 received through the AND 8 element records the data in unit 1 at formation-, m a counter, 12, After zapiei; 5 trailing edge signapa on output of the AND element 9 is added to the contents of the counter unit 12 We write address. si and through the element IL11-14 to the contents of the volume counter 18,

When reading the information received in block 1, the low level signal at the output of the And 7 element provides a connection to the address inputs of the block 1 bits of the counter 13 reading address. When the signal arrives at input 26, the contents of the counter 3 address of the reading address are added, i.e. . on the address input of block 1, the current reading address is set, and the value of the volume counter 18 is reduced by one.

The signal at the output of the one-shot 17 opens a group of elements And 15, carried out the issuance of data on the information output 21 of the device. From the output 45 of the delay element 16, the signal arrives at the output 22 and informs the receiver about the presence of data at the output 21, When it arrives at the information

the delay element 5 and the one-shot 6 write data to block 1. At the falling edge of the signal at input 30 through the open element 10, the content of the address 13 decreases by one unit and the volume 18 increases by the OR element 14 of the content of the counter 18.

The decoder 19, until the memory block 4 is filled, generates the Empty signal at the output 23, and when filled, forms the Polon signal at the output 24,

During the processing of information read by the receiver, it may be necessary to promptly exclude information on priority messages previously recorded in memory block 4, enter information about new priority messages, or enter information about messages that should not be allowed to be processed. At this input 28, a high level signal is set, switching the memory block 4 to the recording mode. The signal at input 25, in accordance with the addresses set at input 27, records new information received at input 29. The information recorded in memory 4, which is output to the first output, is used to block the recording of messages, not additional to processing. At the end of the recording, input 1 is set to 1 low level signal.

Sending this, when information is received at information input 20, which should not be allowed to be processed, the first output of memory 4 sets the signal of the misc level that blocks the recording of this information; in block 1 it blocks the change in the state of the counter 12 of the recording address and counter 18 volume.

thirty

35

40

Claims (1)

Invention Formula A device for coupling the source and receiver of information comprising the information input 20, which requires the priority jg, the first memory block, the first multi-pass transmission, the first output blocker, the write address counter, the memory counter 5 sets a high level, and the second output a low level. The low level at the output of the And 7 element provides a connection through the first multiplexer 3 to the ADR inputs of the block 1 of the signals from the outputs of the counter 13 of the reading address. The signal at the input 30 through the element IV address address bar, volume counter, decoder, three AND elements, OR element, NOT element, two one-shot, two delay elements, AND group of elements, and the information in the first memory block is the input of the device connected to the first information output of the source iy20 j Q t5,; 5 " 45,928 the delay element 5 and the one-shot 6 write data to block 1. At the falling edge of the signal at input 30 through the open element 10, the content of the address 13 decreases by one unit and the volume 18 increases by the OR element 14 of the content of the counter 18. The decoder 19, until the memory block 4 is filled, generates the Empty signal at the output 23, and when filled, forms the Polon signal at the output 24, During the processing of information read by the receiver, it may be necessary to promptly exclude information on priority messages previously recorded in memory block 4, enter information about new priority messages, or enter information about messages that should not be allowed to be processed. At this input 28, a high level signal is set, switching the memory block 4 to the recording mode. The signal at input 25, in accordance with the addresses set at input 27, records new information received at input 29. The information recorded in memory 4, which is output to the first output, is used to block the recording of messages, not additional to processing. At the end of the recording, input 1 is set to 1 low level signal. Sending this, when information is received at information input 20, which should not be allowed to be processed, the first output of memory 4 sets the signal of the misc level that blocks the recording of this information; in block 1 it blocks the change in the state of the counter 12 of the recording address and counter 18 volume. thirty 35 40 Invention Formula the first memory block, the first multihexor, the write address counter, the address of the address of the screen, the volume counter, the decoder, the three AND elements, the OR element, the HE element, two single vibrators, two delay elements, the group of AND elements, and the information block of the first block the memory is the input of the device connected to the first information output of the source 515 the formations, outputs of elements AND groups form a group of outputs of the device for connection to the group of information inputs of the receiver of information, output; The first delay element is the output of the device for connecting to the gate input of the information receiver, the first and second outputs of the decoder are the outputs of the device for connecting readiness of the receiver and source of information respectively, the input of the count increment of the read address counter is connected to the start input of the first one-shot the counting of the volume counter and is the input of the device for connecting to the reading output of the receiver of information, and the information input of the decoder is connected to the output of the volume counter, the input of the increase in the account of which coezjjiHeH with the output of the element OR, the first input of which is connected to the output of the first element AND and the input and the input of the first delay element j the input / write input of the first memory block is connected to the output of the second one-way one, the start input of which is connected to the output of the second delay element, characterized in that, in order to extend the functionality by providing an operative changing the priority of input information and excluding unnecessary information from processing, the second memory block, the second multiplexer, the fourth AND element are entered into the device, the first information input of the second multiplexer, sync The d and information inputs of the second memory block are the device inputs for. connecting, respectively, to the address output, the synchronous clock and the second information output of the information source, the control input of the second multiplexer is connected to the write input of the / / reading of the second memory block and increase the count of the address counter record-25 with the input device to connect CI, the output of which is connected to the first information input of the first multiplexer, whose control input is connected to the output of the second element AND, the first input of the first element AND and the input of the element NOT, the output of which is connected to the first input of the third element AND, the output of which is connected to the second input of the element OR and the decrement input of the counter of the reading address, the output of which is connected to the second information input of the first multiplexer, the output of which is connected to the address input of the first memory block, a group of information inputs which is connected to the first inputs of the AND group whose second inputs are connected to outputs of the first monostable 0 To the information source write / read output, the first input of the second element I is connected to the first input of the fourth element I and is the input of the connection device to the gate output of the information source, while the information input of the first memory block is connected to the second information input of the second multiplexer, the output of which is connected to the address input of the second memory block, the first and second information outputs of which are connected respectively to the second inputs of the fourth and second And elements, the output of the fourth element And is connected to the input of the second delay element and the second inputs of the first and third elements I. 0 w & - at H 6 25 29 L / h 12 3Q  / v / P /five 21 l- f6 22 / V , /four  I- Id nineteen 23 f4