SU1282147A1 - Device for controlling memory access - Google Patents

Abstract

The invention relates to the field of digital computing, in particular to devices for interfacing memory, and can be used to build systems with fast memory. The aim of the invention is to expand the functionality of the device by organizing priority according to the information recording cycle. The device comprises a control unit, an address generation unit, a zone generation unit and a memory unit. The control logic of the device provides a higher priority for the write signals to the memory compared to the read signals from the memory while both signals are received. 2 hp f-ly, 1 ill.

Description

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The invention relates to digital computing, in particular to devices for interfacing with memory, and can be used to build systems with fast memory.

The purpose of the invention is to expand the functionality of the device by organizing the priority of the information recording cycle.

The drawing shows a diagram of the device.

The device comprises an address generation unit 1, a zone fixation unit 2, a pulse generator 3, a memory block 4, a control unit 5, a pulse distributor 6, informational input 7 of the device.

The address generation unit 1 contains the 7KIT first counter 8, the second counter 9, the switch 10, the element OR NOT 11.

Unit 2 fixing zone contains the trigger 12 and the element 13 unequalities.

The control unit 5 contains the fourth 14, five more, the first 16, the second 17, the third 18 flip-flops, the first 19-. and the second 20 elements AND-NOT, the element STI-NOT 21,

The device works as follows.

Block 5 generates a sequence of control signals that implements a given algorithm (write-read) of working with memory. The block 5 is synchronized by the distributor 6 and the generator 3. The distributor 6 is a trigger shift register, which is driven by a series of pulses from the output of the generator 3. A single sweep of the distributor 6 constitutes a synchronization cycle, which may include various the number of clock signals, for example, four: SI 1, ..., SI 4.

The information to be recorded in block 4 is associated with a trigger at the input of the device and, if necessary, can be synchronized with a signal from the output of trigger 14 5. The trigger is also used to set counters 8 and 9.

Information removed from block 4 in the read cycle can be synchronized by a signal from the output of the OR-NOT element 21 block 5.

Synchronization of input and output information can be implemented using i-triggers.

The distributor 6 is installed

in the initial state when power is applied.

The initial state of the distributor 6 corresponds to a single potential of the SI signal 4, which sets the triggers 16 and 17 to a single state, which corresponds to a positive potential at their single outputs. Positive potential from trigger output 16 opens to

one of the inputs is an AND-NOT element 20 and sets the trigger 18 to the zero state, which corresponds to the potential at its inverse output, this shading is forbidding

write cycle in block 4. A single potential from the direct output of trigger 17 is fed to the input of element 13, the level of the signal from the output of which determines the zone of writing or reading.

The trigger signal, appearing at the input of node 2, overturns trigger 12, thereby changing the recording zone to the read zone.

From the outputs of the generator 3, the C-inputs of the flip-flops 14 and 15, respectively, receive pulses of the write and read frequencies.

Priority of block 4

have write frequency pulses. Thus, if the write and read frequency pulses arrive simultaneously, both the flip-flops 14 and 15 are tilted to a single position, while the unit potential remains at the output of the element 20, and the potential of the element 19 appears at the output of the element 19. - trigger input 16. Thus, when the sync pulse SI 1 appears at the C input of the triggers 16 and 17, the trigger 16 is tilted to the zero position, and the trigger 17 remains in the single position.

A single potential from the inverse output of the trigger 16 enters the block 1 and through the element 11 enters the input of the block 4, and also through the switch 10 connects the code of the write address of the counter 8 to the address inputs of the block 4.

A single potential from the inverse output of the trigger 16 resets the trigger 14 to its original position, as well as arrives at the D input of the trigger 18 and with the arrival of the sync pulse SI 2 from the distributor 6, the latter tilts to the single position.

The zero potential arising on the inverse output of the trigger 18 is fed to the corresponding input of block 4, recording information on the D1-input of block 4,

The SI 3 clock pulse, which can be used to synchronize information from the DO output of block 4, will not be output to block 5, since element 21 is closed by zero potential from the inverse output of trigger 17.

The next sync pulse SI 4 sets the triggers 16 and 18 to the initial state, while the pulse drop on the unit output of the trigger 18 changes the code of the record in the counter 8. Now in the next cycle of operation of the distributor 6 with the appearance of the synchro pulse SI 1 the process reading, so as the D-input of the trigger 17 receives a zero potential from the output of the element 20, and a single potential is stored at the D-input of the trigger 16.

Thus, the SI sync pulse of the next cycle overturns trigger 17 to the zero position, while trigger 16 remains in the single position. The SR 2 sync pulse retains a single ini cial pulse at the inverse trigger output 18.

A single potential from the inverse output of the trigger 17 resets the trigger 15, enters unit 1, switches 10 through the switch address code of the counter 9 to the address inputs of block 4 and selects the memory unit through element 11, while at the DO output of block 4 Readout information, which can be synchronized, if necessary, by the sync pulse SI 3, which is fed to the output of block 5 through element 21.

 The SR 4 sync pulse sets the trigger 17 to its initial position, while the pulse on its inverse output causes the read address code in counter 9 to change.

Claims (3)

1. A memory access control device comprising a control unit, a pulse generator and a pulse distributor, with the first to fourth outputs of the pulse distributor connected to the inputs of the first to quarter of the control unit, the clock input of the pulse distributor connected to the first output of the pulse generator, different the fact that, in order to expand the functionality of the device by organizing the priority of the information recording cycle, an address generation unit and a zone fixation unit are entered into it, What is the reset input of the address shaping unit and the triggering input of the zone fixing unit connected to the device launch input; the clock input of the address shaping unit is connected to the first output of the control unit, the address and gating outputs of the address shaping unit and the output of the zone fixation unit are connected respectively to the lower bits of the address input , to the module selection input and to the high-order bit of the address input of the memory unit, the second and third outputs of the pulse generator are connected to the fifth and sixth inputs of the control unit, from the second to the fifth whose output / s are connected respectively to the output of the device for connecting, to the read input of the memory block, the first and second strobe inputs of the address forming unit and to the control input of the zone fixation unit, the zone fixation block containing the trigger the block is connected to the trigger input of the trigger, the zero output of which is connected to the first input of the inequality element, the second input and output of which are connected respectively to the control input and the output of the block. 2. The device according to claim 1, characterized in that the control unit comprises first to fifth triggers, a first, second AND-NOT element and a STI-NOT element, the first input of the unit being connected to the synchronization inputs of the first, second triggers, the second, the third block inputs are connected respectively to the synchronization input of the third trigger and to the first input of the element OR NOT; the direct and inverse outputs of the third trigger are connected respectively to the first, second outputs of the block; the inverse output of the first trigger is connected to the information input of the third trigger At the reset input of the fourth flip-flop and with the third output of the block, the second output flip-flop output is connected to the second input of the OR-NOT element, to the reset input of the fifth flip-flop and to the quarter output of the second flip-flop connected to the first input of the first item AND-NOT and with the fifth output of the block, the fourth input of the block is connected to the single inputs of the first, second triggers, the fifth, sixth inputs of the block are connected to the synchronization inputs of the fourth and fifth triggers, the fourth and fifth triggers are connected to w logical unit, the output of the element OR is NOT connected to the sixth output of the block, the single output of the fourth trigger is connected to the seventh output of the i block and the second input of the first NAND element, the zero output of the fourth trigger and the single output of the fifth trigger are connected respectively to the first and second inputs of the second NAND element, the third input of which is connected to the single output of the first trigger and fO the reset input of the third trigger, the outputs of the first and second elements AND IS NOT connected respectively with the information inputs of the first and second triggers. 3. The device according to claim 1, about tl and - that the block forming the address contains the first, second counters, the switch and the element OR NOT, and the reset input is connected to the reset inputs of the first, second counters, clock input and address and The gate outputs of the block are connected respectively to the counting input of the first counter, to the output of the switch and to the output of the OR-NOT element, the second gate input of the block is connected to the counting input of the second counter, to the first control input of the SH-NOT, whose second entrance and the second control input of the switch is connected to the first gate of the block, the outputs of the first and second counters are connected to the first, second information inputs of the switch. five 20  With Cfl g SI with I