SU1755288A1 - Interface - Google Patents

Abstract

The invention relates to automation and computing and can be used to interface two different processing devices. The purpose of the invention is to simplify the device by using a single counter to set write and read addresses. The device contains a counter, a memory block, an OR element, a trigger, a register, a comparator. 1 il.

Description

The invention relates to automation and computing and can be used to interface two differently sized data processing devices.

The purpose of the invention is to simplify the device by using a single counter to set the write and read addresses.

The drawing shows the functional diagram of the device

The device contains (Fig. 1) counter 1, memory block 2, element OR 3, trigger 4, register 5, comparator 6, information output 7 and input 8, write lock output 9, synchronizing input 10, initial setting input 11, 12 read locks, write inputs 13 and read 14.

The device works as follows.

To bring the device into operation, input 11 receives a signal from the initial installation of the CN. According to it, the counter 1 and the register 5 are set to the zero state. In equality, codeosis at the inputs of the comparator b, it outputs a signal to output 12, thereby blocking the arrival of a reading pulse in the device.

By the write pulse of the ZP at the input 13, the trigger 4 is set to state 1, allowing writing to the memory block 2. The information enters the device at input 8 and is accompanied by SI sync pulses at input 10 and is recorded in block 2. Recording in block 2 is performed at the address corresponding to the state of counter 1. After the current information byte is written, counter 1 is modified on the falling edge of the SI. After that, respectively, the comparator 6 removes the read lock signal. After going through all of their code combinations, counter 1 sets a transfer system at output 9, thereby blocking further recording of information in the device.

When reading information on the input 14 signal is received THU. According to it, trigger 4 is set to O and writing to block 2 is prohibited. The OR 3 elements generate a write signal to counter 1 and register 5. Register 5 contains the last write address, counter 1 the last read address, and in this case, zero. The SI starts reading the information recorded in block 2. It enters output 7. When switching to the write mode, the element OR 3 impulses the RFP again generates a write signal, and the last write address is entered into the counter, and the last read address is entered in the register. When establishing the equality of the codes at the information outputs of the counter 1 and register 5, the comparator 6 again issues a read blocking signal. In the presence of blocking signals at outputs 9 and 12, operation of the device can be resumed by issuing a signal WELL.

In this way, information is recorded and read from the device in conjunction with the pairing of two different-rate information processing devices.

Claims (1)

Claims An interface device comprising a counter and a memory block, the output and information input of which are respectively, the information output and input of the device, and the address input is connected to the information output of the counter, the transfer output of which is the write lock output of the device, and the counting input and the reset input are (with, respectively, the synchronization and initial installation of the device, so that, in order to simplify device, it contains an OR element, three rp, a register and a comparator, the output of the comparator is the read lock output of the device, the first input is connected to the register output and the information input of the counter, and the second input is connected to the information output of the counter and the information input of the register the reset of which is connected to the input of the initial installation of the device, and the synchronous input to the input of the device's counter and the output of the OR element, the first and second inputs of which are respectively the recording and reading inputs of the device and connected to tvetstvenno to set and reset inputs of the flip-flop, the output of which soedichei with input of write enable memory zzpmsi input of which is connected to the clock input ustroystga.