SU1418691A1 - Data input device - Google Patents

Abstract

The invention relates to digital computing, in particular to devices for interfacing switching elements with digital equipment, and is intended for manual entry of information. The aim of the invention is to increase the reliability of the device. The device contains a matrix of switching elements, a counter, a decoder, a multiplexer, three triggers, two pulse shapers, and four NAND elements. Achieving this goal is provided by eliminating the possibility of generating spurious recording signals by gating the decoder to the transient time in the counter. In addition, the device allows both single and multiple entry of the key pressed code. The ability to repeatedly enter a key code is determined at the design stage of the device. 2kl. W

Description

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I The invention relates to digital computing, in particular to devices for interconnecting switching elements with digital equipment, and is intended for manual input of information.

The aim of the invention is to improve the reliability of the device.

I Figure 1 shows a diagram of the proposed device; figure 2 - diagrams of the device.

The device contains the first 1 and second 2 elements AND-NOT, the counter 3, the decoder 4, the matrix 5 of the switching elements, the multiplexer 6, the first trigger 7, the first driver 8i pulses, the second driver 9 and "pulses, element 10, the second 11 and | the third 12 triggers, the third 13 and the fourth 14 elements NAND.

I The diagrams (Fig. 2) denote: a - a signal at the clock input of the device, b - a signal at the output of the first element AND – NE 1, c. - NOT 2; d is the signal at the output of the first trigger 7, e is the signal at the second output, the driver 8 pulses; the signal at the first output of the driver 8 pulses, 3 the signal at the output of the driver 9 pulses, and the signal ya output of the element HE 10; k - signal At the output of the second trigger 11; l - the signal at the output of the third trigger 12I m - the signal at the output of the third element AND-NOT 13.

The pulse shaper 8 is implemented in the form of two serially connected standard multivibrators on 133-A3G chips. As the first output of the driver 8, the output of the first stage is used, the output of which also triggers the second stage, the output of which is the second output of the driver 8.

The pulse shaper 9 is implemented as a trigger on a 533TM2 type microcircuit, the informational D input of which is connected to the zero potential bus of the device. The formation of pulses is carried out by applying to the synchronization input and the input

setting the trigger pulse from the corresponding outputs of the decoder 4. These pulses are selected in each particular case of application

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The proposed device in such a way that at the output of the driver 9 a signal is generated that corresponds to the moments of interrogation of the switching elements, the code (information) of which is required to be written once.

In the initial state, all switching elements of the matrix 5 are in the open state. At the output of the trigger 7, a signal with a level of logical zero is permanently present, which closes the NAND element 2. A logical unit from the output afterwards ensures the passage of clock pulses (Fig. 2a) through the N1 element 1 to the input of the counter 3, - the receiving input of the decoder 4 and the input element AND-NOT 2 (Fig.26). Counter 3 continuously counts the incoming clock pulses, changing the output code with each pulse. At the outputs of the decoder 4, the polling signals of the switching elements of the matrix successively appear. However, the polling signals do not pass through the switching elements of the matrix 5, and therefore the information inputs of the multiplexer 6 also lack the signals indicating the inclusion of the corresponding elements of the matrix 5. The pulse driver 8 in the initial state does not generate output pulses, since the output element of the AND-NOT 2. The imager 9 periodically generates pulses that limit the time of the survey switching elements with a single write (the period is determined by the period of th counter filling 3). Since the input of the unit state of the trigger 11 from the output of the element NOT 10 receives impulses from the output of the imaging unit 9, the trigger 11 is in the unit state, while the output of the trigger 11 uses the inverse output, therefore the signal with the logical zero. Logical zero from the information input of the trigger 12 is recorded (and constantly confirmed) by the output signal of the driver 9. The output of the trigger 12 is the inverse output, so the signal with the level of the logical unit enters the third input of the AND-HE element 13. Since in the initial state at the outputs of the imager 8

the pulses are absent, the AND-HE elements 13 and 14 are closed, and at the first and second control outputs of the nm device there are no information recording pulses (counter code 3).

When the operator switches on one of the elements of the matrix 5, a pulse is formed at the output of the multiplexer 6, which is fed to the input of the trigger setup

7 (FIG. 2c), which is set to one (FIG. 2e).

At the end of the counting pulse (Fig. 26), corresponding to the pulse at the output of multiplexer 6 (Fig. 2b), an AND-HE element 2 is opened, and at its output a voltage drop occurs from the state of the logical unit to the state of logical zero (Fig. 2d). This differential starts the driver

8 pulses, as a result of which at its outputs there appear pulses shifted in time with respect to each other. This is achieved by the fact that a backward pulse front of the first cascade (Fig. 2g) of serially connected waiting multivibrators entering shaper 8 is triggering for the second cascade. The output pulse (Fig. 2g) of the first cascade of the imaging unit 8 is fed to the first inputs of the third 13 and fourth 14 AND-NOT elements. Depending on the hit

Within the limits of the pulses at the output of the former (FIG. 2c - lower level), the counter 3 code is written into the corresponding external device. Diagrams h, u, k, l, m (phi1 .2) represent the case when the interrogation signal corresponds to a single record and passes through the IS-NE 13 element (fig.2m). On the trailing edge of the pulse (Fig. 2e), the trigger 7 returns to the initial (zero) state (Fig. 2e), and the trigger 11 records information about the location of the polling pulse (Fig. 2b) in the write-once zone. Since the output signal of the trigger 11 is removed from the inverse output, the level of the logical unit is formed (FIG. 2k). At the time of the termination of the write-once pulse (Fig. 2h), the logical unit from the output of the trigger 11 is written to the trigger 12, and the output signal of the trigger 12 is removed from the inverse output, so a logic zero appears at its output (Fig. 2) . Specified level

(Fig.2l) closes the element AND-NOT 13 and prevents the re-formation of the recording signals to an external device. This is achieved by the fact that in the next polling cycle of the included element of matrix 5, the writing of the logical unit (Fig. 2k) to the trigger 12 is confirmed, i.e. the level of logical zero (FIG. 2l) at the output of the specified trigger is maintained. In the proposed device, the polling signals at the output of the decoder 4 are gated by the input signals of counter 3, which eliminates the possibility of spurious impulses at the inputs of multiplexer 6, trigger 7, AND-NOT 2, imaging unit 8, and AND-NOT elements 13 and 14, therefore synchronizing recording output pulses of elements AND-NOT 13 and 14 do not contain false pulses.

Claims (1)

Invention Formula A device for entering information, containing a matrix of switching elements, a counter, a decoder, a multiplexer, two NAND elements, the first input of the first NAND element is a clock input of the device, the output of the first NAND element is connected to the counting input of the counter and the first input of the second the NAND element, the output of which is connected to the second input of the first NAND element, the counter outputs are connected to the information inputs of the decoder and are the information outputs of the device, the high bits of the counter are connected to the address the multiplexer inputs, the decoder outputs are connected to the matrix inputs of the switching elements, the outputs of which are connected to the information inputs of the multiplexer, which is because, in order to increase the reliability of the device, three triggers are introduced into it, the third and fourth elements are NAND, two pulse generator and the NOT element, the gate of the decoder is connected to the output of the first NAND element, the multiplexer output is connected to the installation input of the first trigger, whose information input is connected to the zero potential bus The device, the input of the first pulse generator is connected to the output of the second NAND element, the second output of the first pulse driver is connected to the synchronization inputs of the first And: the second trigger, and its first output - with the first inputs of the third and fourth elements IS-IE, aiixofl of the first trigger is connected to the second input of the second element AND-NOT, the inputs of the second pulse generator are connected to the outputs of the decoder, output | ed of the second generator pulses connected to the information input of the second | ego trigger, the synchronous input of the third t of the zigger, the second input of the fourth the AND-NOT element and through the NOT element with the installation input of the second trigger and the second input of the third AND-NOT element, the output of the second trigger is connected to the information input of the third trigger, whose output is connected to the third input of the third AND element, whose output is the first write output of the device, the output of the fourth AND-NO element is the second write output of the device. FIG. / a 6 . and