SU1633387A1 - Data output device - Google Patents

Abstract

The invention relates to the field of automation and computer technology and is supposed to be used to output data from slots i from reading machines for the purpose of promptly displaying them on screens of electron-beam: tubes. The purpose of the invention is to improve the accuracy of the device, by introducing a code word analyzer and corresponding functional links. The invention makes it possible to use the basis of Walt functions when displaying graphical information with a higher order with a fixed memory space and thereby increase the accuracy of displaying graphical information by 15%. 2 etc F-ly, 4 Il.

Description

The invention relates to automation and computer technology and can be used to output data from computers with a chain of their operative branch, ARMY on the screens of electron beam tubes.

The invention of the invention - improving the accuracy of the device.

Figure 1 shows the functional diagram of the device; in FIG. - Functional diagram of the control unit; on fig.Z - functional scheche code word analyzer; figure 4 - timing diagrams of the code word analyzer.

The device contains, for each of the coordinates X, Y, the control unit D control unit. Reg. 2, the generator 3 Walsh functions, the converters 4.1–4. N code-voltage, the modulators 5.1–5. N, the adder 6, CRT 7, the analyzer AND code words .

The control unit 1 is designed to control the operation of the code word analyzer 8, to control the reading of the full information code from the register, to control the operation of the generator 3 of the Wulp functions. The control block 1 contains the first key 9, the first counter 10 (modulo N (n-H)), the clock pulse generator I 1, the second key 12, the second counter 13 (modulo 1), the third key 14, the fourth key 15.

Register 2 is designed to record the full information code coming from the analyzer 8 code words.

The Walsh function generator 3 is designed to generate Walsh functions and pulse-end pulse generation (ICC).

oh

CO CO CO 00

vj

The 4.1–4.N code-to-voltage transducers are designed to convert the values of the complete information code from register 2 to a voltage proportional to the Walsh coefficients (CJ).

The modulators 5.1-5.N are designed to modulate the amplitude of the Walsh functions in accordance with the values of the coefficients C1.

Adder 6 is designed to form a control voltage, which is the sum of the amplitude-modulated Walsh functions (W; (t)):

N-t

U (c)

W

j (t) -C; (t),

Where

 2

-P

NI

W; (t) II (C)

Q

g

0

five

de element 17 of the delay; 31 — overflow pulses at the P output of counter 22; 32 - pulses nl direct input of the third trigger 26; 33 - pulses at the inverse input of the third trigger 26; 34 - pulses at the first input of the decoder 28; 35 - pulses at the second input of the decoder 28; 36 - pulses at the third input of the decoder 28; 37 - pulses at the direct input of the first trigger 18; 38 - pulses at the inverse input of the first trigger 18; 34 - pulses at the first output of the decoder 28; 40 — impulses at the second output of the decoder 28; 41 - pulses at the clock output of the analyzer 8 code words; 42 - pulses at the information output of the analyzer P code words.

The device works in the following way.

Many decomposition coefficients C; over the basis of functions, walsh is represented by a combination of the following two subsets:

CRT 7 is designed to display graphic information. The output of the horizontal deflection system (not shown) of the CRT 7 is connected to the output of the adder 6 of channel X. The input of the vertical deflecting system of the CRT 7 is connected to the output of the adder 6 of the channel Y.

The code word analyzer 8 is intended to determine the significant and zero combinations of the incomplete information code, which composes legal information models, and also to form a complete information code followed by writing to the register. The analyzer 8 code words contains the first element OR 16, the delay element 17, the first trigger 18, the first element AND 19, the register 20, the second trigger 21, the counter 22, the second element II 23, the second element OR 24, the third element OR 25, the third trigger 26, the third element And 27, the decoder 28.

For simplicity of the explanations, the dimension of the basic system of the Volpe functions is chosen equal to 128 (N 2П 27). As an example, an incomplete information code is used, which looks like: 1 0101001 О О 1 1011001 ...

In Fig. 4, the following designations are accepted: 29-pulse pulses at the output of the generator; 11 clock pulses; 30 - clock pulses on the output

(S

5 0 5

0

five

Where

WITH

Yu

Ci are significant decomposition coefficients;

- zeroed decomposition coefficients, the values of which do not exceed the specified

zero threshold, f

Each significant equivalent of the decomposition coefficient from a subset of Gs. | it is necessary to assign an additional one-bit, resulting in a significant codeword. The collection of character codewords is an incomplete information code. In addition, zeroing out the coefficients from the subset fCj0l in the incomplete information code corresponds to zero bits, which allows determining the position of the zero coefficient in the total sequence of expansion coefficients.

At the information model synthesis stage, each significant code word is processed in the code word analyzer, as a result of which additional bits are eliminated, after which the significant equivalents of the decomposition coefficients are written to the register. At times corresponding to zero additional bits, the code word analyzer writes to a register of zero equivalents of decomposition coefficients.

The result of the operation of the code word analyzer is the full information code of the information model component recorded in the register.

The device works as follows.

According to the preliminary command, the information in the form of an incomplete information code 101010010 01 is fed to the information input of the device and to the information input of the register 20 of the analyzer 8 code words. At the same time to the input of the C2 register 20 receives the enabling signal. Register 20 records an incomplete information code.

In the initial state, the elements of the analyzer 8 code words are in the following position. At the direct output of the first trigger 18 there is a single potential, at the direct output of the second trigger 21 there is a zero potential. The binary counter 22 contains the number (111). The inverse output of the third trigger 26 has a high potential. On the first and second outputs of the decoder 28 unit potentials are absent.

At the initial moment of time, a short end of flow appears at the control output of control unit 1. cycle (ICC), which in control block 1 comes from the corresponding generator output 3 of the Waschy functions. Under the action of the CSC register 2 is set to its original position - zero. In this case, in block 1 of control (Lig.2), counters 10 and 13 are set to the initial state, keys 9 and 12 are opened. The clock pulse generator is triggered by a signal received via the Start bus. Clock Sequence c. the output of the clock generator 11 is fed to the information input of the first batch 9 and through the first clock output of the control unit 1 to the information input of the analyzer 8 codewords. At the same time, the clock pulses from the output of the key 9 arrive at the information input of the counter 10.

The first clock pulse entering the code word analyzer 8 is delayed by a delay element 17

time cv, which is necessary for cf-

33876

the second counter 22 and the switching of the third trigger 26, and then goes to the first input of the first element And 19. From the output of the first element II 19, the first clock pulse goes to the second input of the third element WIT 25 and to the synchronous input C1 of the register 20. The first element of the incomplete information code 1 appears at the output of register 20, passes to the third input of the decoder 28 and to the information output of the analyzer 8 codewords.

The first clock pulse of the clock sequence from control block 1 also enters the counting clock.

ten

15

/ G-TOP BINARY Counter

t

in which

five

0

five

0

five

0

five

rum recorded number (111). On this impulse, the binary counter 22 is zeroed, an overflow pulse appears at its KE HODS reamoutment P, which is noc ivnaeT at the first input of the first OR 16 element and at the P input of the third trigger 26. Under the action of the first clock pulse arriving at synchronization C of the second flip-flop 26, at the direct output of this flip-flop appears the logical I value, which goes to the second input of the decoder 28. The zero potential from the inverse output of the third flip-flop 26 goes to the second input of the third element II 27, to the first input of which The first sync pulse from the output of the third 1GSh ° 5 element. When this clock pulse from the output of the first element II 19 does not pass to the output of the analyzer 8 code words, and the zero potential from the output of the third element And 27 goes to the first input of the decoder 28. Thus, the three inputs of the decoder 28 have an input combination (011). The value 1 of the incomplete information code is not recorded in register 2 (FIG. 4, point in time c).

The logical 1 signal from the first output of the decoder 28 is fed to the first input of the first element OR 16. Under the action of the unit potential from the direct output of the first trigger 18 and the clock pulses of the clock sequence of the control unit 1, the synchronization pulses go through the first element 19 of the register 20 The next (second) value O of the incomplete information code appears on the output of register 20. This value O comes to the third input of the decoder 28 and then to the information output of the analyzer 8 code words.

At this time, the binary counter 22 counts the incoming

"

counting clock pulse input. On the bit outputs of the binary counter 27, there are single signals, which through the second element OR 24 arrive at the P input of the third flip-flop 26. At the direct output of the third register 26 there appears a zero potential. The logical zero signal from the direct output of the third trigger 26 is fed to the second input of the decoder 28, and the logical 1m signal from the inverse output of the third trigger 26 is fed to the second input of the third element I 27 and under the action of the synchronization pulse from the output of the first element H 19 8 code words pass through the third element OR 25 to the clock output of the analyzer. This logical 1 signal also arrives at the first input of the decoder 28. At the three inputs of the decoder 8 there is an input combination (100). However, no decision is made on this combination. At the same time, the value of logical O from the output of register 18 under the action of a synchronization pulse from the output of the third element And 27 is written to register 2. A similar situation occurs at times n - c7 (Fig. A), i.e. when at the first input of the decoder 28 there is a logical value of 1. At times t, tg, t, 6, t g,. . . At the first input of the decoder 28, under the action of the enable signal of the binary counter 22, the logical O signal is present. At these times, the values of the incomplete information code from register 20 are not recorded in register 2.

At time t, the value of the incomplete information code O from the output of the register 20 is fed to the third input of the decoder 2H. This value of zero bit carries information with zero code in the word that should be written to register 2. According to

the action of the enable signal of the binary counter 22 at the clock output of the analyzer 8 code words appears logical value O, which

5 0 0

five

arrives at the first input of the decoder 28. To the second input of the decoder 28, a signal 1 is sent from the direct output of the third trigger 26. The input combination (010) of the decoder 28 allows to receive at its second output a logical 1 signal, which is fed to the R input of the first trigger 18 and puts it in the zero state. Further reading of the incomplete information code from the register 20 is terminated. Along with this, the signal of logical 1 from the second output of the decoder 28 is fed to the S input of the second trigger

21 permits the passage of clock pulses from the output of the delay element 17 through the second element AND 23, the third element OR 25, and also the third element AND 27 at the clock output of the analyzer 8 code words. At times with - with ,. A zero codon word is written to register 2, consisting of seven logical O. At the time point, a binary counter

22 gives the enabling pulse, by which the first trigger 18 passes

in the one state, and the second trigger 21 - in the zero state. The next clock pulse of the clock sequence through the first element 19 is fed to a snoop input C1 of the register 20. At the output of the register 20, the next value of the incomplete information code appears - logical O. In this case, the input combination of the decoder 28 is a combination of the form (010), which will be In the analyzer circuit, there are 8 code words at times t - as well as at times t with q - t.

time point with

24

At the output of register 20, the value of logical 1 appears. It is not recorded in register 2, however, at times t - c, code word 1011001 is written to register 2. Analyzer 8 code words function as long as significant words of an incomplete inLormatical code from register 20 will not be written in register 2.

In control block 1, when 10 N (n + 1) pulses arrive at the counter, a logical O appears at its inverse output, which closes key 9, and at the forward exit, logical 1, under the action of which key 14 opens, allowing the clock flow to pass. impulse through open

the key 12 to the read input of the register 2, and the clock sequence to the information input of the counter 13.

The outputs of register 2 are divided into groups. Each group of these outputs corresponds to a code of a single value of C /. Under the influence of the contents of the reg

country 2 with the output of 4.1-4.N converters, the voltage is removed, the value of which is proportional to C.

When a pulse arrives at the counter, a logical O appears at its inverse output, which closes the key 12, and at the forward output - logical 1, under which the key 15 opens and the sequence of clock pulses through the public key 15 is fed to the clock input of the generator 3 wapt functions, the latter is launched.

On each 5.1-5.N modulator, a potential signal C arrives at one input; and the corresponding j-Walsh function is selected at the second. The outputs of the modulators 5.1-5.N are used to remove the functions of Walt, which are modulated in strict accordance with C. From the output of the adder 6, the control voltage is removed, which determines the sum of the amplitude-modulated functions of Walt modulated by the amplitude. The DTO voltage is supplied to one of the deflection systems of a CRT 7.

At the end of one period, the Walsh function from the output of the generator 3 Walsh functions, the ICC signal is taken, which is fed to the input of control block I.

Thus, in the proposed device, by using the basis of the Washch functions, a higher order with a fixed memory size, it is possible to increase the accuracy of displaying graphical information models by 15%.

Claims (3)

1. A device for displaying information on the screen of a cathode ray tube containing, for each of the coordinates X, Y, a control unit, a register, a Walsh function generator, code-voltage transducers, modulators, an adder, the flow of the control unit connected to the output of the generator Walsh function torus, the first output of the control unit is connected by a g. About the register, second exit 10 15 20 25th day ) five 40 45 50 55 The control unit is connected to the control input of the register, the third output of the control unit is connected to the input of the generator of the Walsh functions, the converter inputs are code-voltage connected to the bit outputs of the register, the control inputs of the modulators are connected to the outputs of the corresponding code-voltage converter , the information inputs of the modulators are connected to the corresponding outputs of the generator of the Walsh functions, the outputs of the modulators are connected to the corresponding inputs of the adder, the output of the adder is connected to the deflection system of a CRT, In order to improve the accuracy of the device, the code slop analyzer is introduced into it, the clock input of which is connected to the fourth output of the control unit, the information input of the code word analyzer is the information input of the device, and the output of the code word analyzer is connected to the snxr input register, the second output of the code word analyzer is connected to the information input of the register. 2. The device according to claim 1, of which is that the code word analyzer contains the first OR element, the delay element, the first trigger, the first AND element, the register, the second trigger, the counter, the second AND element, the second OR element, the third element OR, the third trigger, the third element AND, the decoder, the synchronization input of the third trigger is the clock input of the analyzer and is connected to the counting RCDM counter and the input of the delay element whose output is connected to the first inputs of the first and second elements II, the output of the second element and connected to the first input for the third OR element, the second input of which is connected to the output of the first AND element connected to the synchronous input of the register, whose information input is the information input of the analyzer, the output of the third OR element is connected to the first input of the third AND element, whose input is the first analyzer output and connected to the first input of the decoder, the second and third inputs of which are connected respectively to the direct output of the third three: throats and the register output, which is the second output of the analyzer, the first, second and the third bit outputs of the counter are connected to the corresponding inputs of the second element OR, the output of which is connected to the input of Set. About the third trigger, the inverse output of which is connected to the second input of the third element I, the overflow output of the counter is connected to the input Set 1 of the third trigger, to the inputs of the Set About the counter, the second trigger and to the first input of the first element OR whose output is connected to the input Set 1 of the first trigger, the output of which is connected to the second input of the first element I, the first output of the decoder is connected to the second input of the first element OR, the second output of the decoder is connected to the input of the Set O of the first trigger and input Set. 1 second trigger, the output of which is connected to the second input of the second element I. 3. The device according to claim 1, characterized in that the control unit contains the first key, the first counter, the clock pulse generator. five 0 five owls, second key, second СЧРТЧИК, third and fourth keys, entrance Set. The first counter is the input of the unit and is connected to the input of Set. P of the second counter, the gate is south (the first output of the block, the clock generator input is connected to ITHHOH Start, and the pulse generator output is connected to the information inputs of the first and third keys, the third key output is connected to the information inputs of the second and fourth keys, the output of the second key is The second output of the block and connected to the information input of the second counter, the inverse and direct outputs of which are connected respectively to the control inputs of the second and fourth keys, the output of the fourth key is the third The output of the block, the output of the first key, is the fourth output of the block and is connected to the information input of the first counter, the inverse and direct outputs of which are connected respectively to the control inputs of the first and third keys. Fig 2 Fig.Z And SS5 "3 S3fcS335P about