SU1656513A1 - Framing word extractor - Google Patents

Abstract

The invention relates to automation and computing and can be used in receiving units of binary processing systems for synchronizing the reception of a continuous digital stream divided into information frames. The aim of the invention is to reduce the search time of the personnel sync word. The goal is achieved by introducing an address counter 3, a memory block 22, an AND element 9. of the element OR 12, a switch block 17. 2 Il.

Description

The invention relates to automation and computing and can be used in receiving units of binary information processing systems for synchronizing the reception of a continuous digital stream divided into information frames.

The purpose of the invention is to reduce the search time of the frame sync word.

Figure 1 shows the block diagram of the device; figure 2 - diagram of the code generator.

A frame sync word (KCC) selection device contains a frame format counter 1, a code generator 2, an address counter 3, triggers 4 and 5, single-oscillators 6 and 7, elements AND 8-11, elements OR 12.13 and 14. element 15 adding modulo two, error counter 16, switch block 17, clock input 18, setup input 19, frame termination output 20, information input 21, memory block 22.

Code generator 2 contains AND 23, shift registers 24 and 25, modulo two addition element 26.

In the initial state, the counter 3 of the address is held in the zero state by the signal from the output of the trigger 4. About the trigger 4 and 5 are in the zero state. The output signal from the inverse output trigger 5 allowed the operation of the code generator 2 and element 9 I was opened. The initial combination corresponding to the length of the additional code (from the frame sync code code) was recorded in the frame format counter 1. At the outputs of one-shot 6 and 7 - the potential of logical zero.

The counter 16 is in the zero state.

To conduct the device to the initial state, when the power is turned on, the initial input signal is applied to the second input of the element OR 14. In this case, the trigger 5 switches to the zero state, and the original combinations are written to the code generator 2 and the frame format counter 1.

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The device works as follows.

The input 21 of the device receives discrete information, which contains the KCC. Each KCC consists of two parts, the division into which is purely conditional. One part is a code sequence formed according to a predetermined law (for example, M is a sequence, a bent function, etc.), and the second part is an additional code composed depending on the selected type of the first part.

When entering into synchronization in the device, an element-by-element comparison of the symbols of discrete information arriving at input 21 with the symbols of the CIL (its first part) is performed. The formation of the first part of the KCC is carried out by the generator 2 of the code, and the elementwise comparison is performed on the element 15 of the modulo two addition. The generator 2 of the code forms at each output each regular symbol at the occurrence of the next clock pulse at the clock input of the device.

If the symbol from the generator 2 output coincides with the symbol coming from the communication channel, then the frame format counter 1 adds one to its state by a clock pulse.

If the characters do not match, a logical unit signal appears at the output of the modulo-two element 15, the opening element AND 10. A decay of the clock pulse at the inverse input of the AND 10 element at its output results in a logical unit signal that through the element OR 13 triggers the one-shot 7. A pulse from the output of the one-shot 7 through the element OR 14, affecting the recording resolution inputs of the generator 2 of the code and the counter 1 of the frame format, brings them to the initial state.

As soon as the KCC appears in the input discrete information, the frame format counter 1 counts to the state corresponding to the KCC length, and a logical unit signal appears at its first output. This signal switches the triggers 4 and 5 to one state. In this case, the signal from the inverted output of the trigger 5 prohibits the operation of the generator 2 of the code, closes the elements 9 and 10, and the signal from the direct output of the trigger 5 opens the elements 8 and 11.

The output signal of the trigger 4, the counter 3 is held in the initial state, and the signal from the inverse output of the trigger 4 closes the element And 11. This state

device allows counter 1 to count

frame length before the appearance of the next KCC.

At the end of the frame length on the second

The output of counter 1 of the frame format appears as a signal that triggers the single-vibrator 6. The duration of the output signal of the single-vibration 6 is selected to be less than half the time period for the symbols of discrete information. The output signal of the oscillator 6 resets to zero the frame format counter 1, the counter 16 errors and switches the trigger 4 to the zero state.

From this point on, a comparison is made of the full reference KCC formed

5 counter 3 and a block of 22 memory, with the KCC. coming to the information input 21 of the device. If any symbols do not match the clock pulse decay, the output signal of a logical unit appears at the inverse input of the OR 11 element. 8, during the KCC reception interval, these signals are summed by counter 16.

If the number of mismatches exceeds a certain threshold value, which is 5 with a sign of loss of synchronization, then a signal appears at the output of counter 16, which, passing through the OR 13 element, triggers the one-shot 7. The output of the one-shot 7 causes the device to return to its initial state whereupon the operation of the device begins again with the search for CSS.

Using the switch block 17, a binary code corresponding to the length of the additional part of the CSS is supplied to the information inputs of the counter 1 of the frame format.

Consider what reduces the time for a KCC search.

Suppose the initial KCC combination (for the prototype) looks like this: 11011100 ...

0 Suppose that in the stream of discrete information before the code KCC were two units. These two units coincide with the first two units that the code generator generates. However, the third comparable symbol from the input stream of discrete information is the first symbol of the KCC, but the comparison is made already by the third symbol of the KCC, formed by the code generator. Coincidentally, this does not happen, the code generator returns to its original state. The true KCC is skipped, and so it is repeated each time while in the input stream of discrete information before

5 KCC will be a character (or set of characters) that matches the initial part of the KCC.

In the device, the generator 2 code forms the second part of the KCC. and counter 3, in conjunction with memory block 22, is a full CIL. Therefore, any, similar to the KCC, combination. turned out to be in front of the KCC, the analysis begins after the arrival of the additional code from the second part of the KCC when it enters synchronization, and only after that, in the process of maintaining synchronism, the complete KCC is analyzed, which forms the counter 3 in conjunction with the memory block 22 ti.

Claims (1)

An apparatus for allocating a frame sync word containing a frame format counter, two triggers, two one-shot, an error counter, a code generator, two AND elements, the first element OR an addition element modulo two, the first bit output of the frame format counter connected to the inputs setting 1 of the first and second triggers, the second bit output of the frame format counter is connected to the input of the first one-shot, the output of which is connected to the reset inputs of the first trigger and error counter, the output is partial which is connected to the first input of the first element OR, the output of which is connected to the input of the one-shot, the counting input of the frame format counter is connected to the clock input of the code generator, to the inverse inputs of the first and second elements AND, and that input of the addition element module two is the information input of the frame sync device, the output of the first element AND is connected to the second input of the first element OR, the output of the second element AND is connected to the counting input of the error counter, the first input The first element And is connected to the first input of the second element And, the inverse output of the first trigger is connected to the second input of the second element And, the third input of which 18 connected to the direct output of the second flip-flop, the inverse output of which is connected to the second input of the first element AND, so that. in order to reduce frame sync word search time, the address counter, memory block, switch block, third and fourth elements I. are entered into the device. second and third OR elements, the counting input of the address counter connected to the clock input of the device, the outputs of the switch block connected to information inputs of the format counter frame, the direct output of the first trigger is connected to the reset input About the address counter, the bit outputs of which are connected to the address inputs of the memory block, the output of which is connected to the first input of the third element I, the output of which is connected to the ps-second input the second: the OR element, the output of which is connected to the second input of the addition element modulo two, the second input of the third element 1 is connected to the direct output of the second trigger, the inverse output of which is connected to the first input of the fourth element I and with the input of blocking the operation of the code generator, the output of which is connected to the second input of the fourth element AND tU.i; the second input of which is the input of the initial installation of the device, the output of the third element OR is connected to the input enable the generator code recording, with the reset of the second trigger and with the frame resolution input of the frame format counter, the reset input of which is connected to the output of the first one-vibrator and is the output sign of the device frame end. srigL