RU2023309C1 - Device for receiving telecontrol programs - Google Patents

Abstract

FIELD: electric communication, pulse-code telecontrol systems. SUBSTANCE: device has storage units 1,2,3, comparison elements 4,5,6, RS-flip-flops 7,8,9, D-flip-flops 10,11,12, AND gates 13,14,15, OR gate 16, control signal shaper 17, shift register 18, OR gate 20, frequency divider 21, reference frequency generator 22, AND gate 23, address counter 24, key code combination storage unit 25, decoder 26, packet counter 27, integrator 28, OR gate 29 and NOT gate 30. The device is characterized in that control commands can be received without preliminary clock synchronization of high-speed transmission. EFFECT: enhanced permissible reception speed. 2 dwg

Description

 The invention relates to telecommunications and can be used in pulse-code telecontrol systems.

 The known device for receiving triply repeated control commands contains three memory blocks, a majority block, two keys, a code sign analyzer, a drive, a decoder, five OR elements, three counters, a distributor and an AND element and can significantly increase the noise immunity of receiving telecommand commands due to majority processing .

 The known device for receiving telecommand commands contains two memory blocks, two counters, four triggers, three inverters, an AND element, an OR element, a shift register, two keys, two decoders, two comparison blocks and allows you to expand the scope of the device by receiving control commands in direct and inverse code.

 A known device for receiving telecommands contains a unit for converting sequential code combinations into control signals, three memory blocks, an integrator, an OR element, a reference frequency generator, a frequency divider, an And element, a counter of bursts of read pulses, an address counter, three differentiating elements, OR elements, RS-trigger and allows you to receive without synchronization on clocks by the method of receiving code signals.

 The disadvantage of this device is the limitation on the speed of receiving telecommand commands, caused by the need for sequential analysis at each clock cycle of receiving a large amount of binary information equal to the number of binary characters in the telecommand recorded in each of the three memory blocks.

 This goal is achieved by the fact that in the device for receiving telecontrol commands, containing an integrator, the input of which is the input of the device, the output is connected to the input of the first memory block, the reference frequency generator, the output of which is connected to the input of the frequency divider, two OR elements, AND element, RS -trigger, control signal generator, address counter, pulse burst counter, memory blocks, output of the first element OR connected to the control signal generator, shift registers, comparison elements, RS-triggers, D-triggers are introduced gers, OR element, and a group of AND elements, a key code combination memory block, a decoder, a NOT element, the first, second, third outputs of the frequency divider through the second OR element are connected to the control input of the integrator, the first output is connected directly to the control inputs of the first, second, and third blocks of memory, to the first input of the third OR element and to the installation input of the pulse packet counter, the second and third outputs are connected to the C-inputs, respectively, of the first and second shift registers, the outputs of which are connected to the inputs the second and third memory blocks, the D-inputs of the shift registers are connected to the integrator output, the output of each memory block is connected to the first inputs of the same comparison element and the same element AND groups, the outputs of the elements AND groups are connected to the inputs of the first OR element, the output of the third OR element is connected through the address counter to the address inputs of the memory blocks, the outputs of the pulse packet counter through the memory block of the key code combination are connected to the second inputs of the comparison elements and directly to the inputs of the decoder, whose first output is connected to the S-inputs of RS-flip-flops and the R-inputs of D-flip-flops and through the element is NOT connected to the first input of the AND element, the second input of which is connected to the reference frequency generator, and the output is connected to the second input of the third OR element and to the counting by the input of the pulse packet counter, the second decoder output is connected to the C-inputs of D-flip-flops, the outputs of which are connected to the second inputs of the elements of the same name and the group of outputs of the comparison elements are connected to the installation inputs R of the same RS-triggers, the outputs of the RS-triggers are connected D-D-inputs of similar flip-flops.

 Figure 1 shows the structural electrical diagram of the proposed device; figure 2 - timing diagrams of the main signals of the device; in FIG. 2A is a plot of the reception frequency F; on figb - the sequence of signals 1, 2 and 3, respectively, at the first, second and third outputs of the frequency divider 21; on figv - packs of pulses received at the input of the address counter 24; on fig.2G - the signal at the first output of the decoder 26, locking the operation of the device; on fig.2D - the signal at the second output of the decoder 26, allowing the passage of the information part of the control command in the shaper 17.

 A device for receiving telecontrol commands contains the first 1, second 2, third 3 memory blocks, the capacity of each of which is equal to n number of binary characters in the telecontrol command, the first 4, second 5 and third 6 comparison elements, RS triggers 7, 8, 9, D-flip-flops 10, 11, 12, group of AND elements 13, 14, 15, first 16 OR element, driver 17 of control signals, shift registers 18, 19, third 20 OR element, frequency divider 21, reference frequency generator 22, first 23 element And, address counter 24 with a capacity of n + 1, block 25 memory key code combination with a capacity of K, where K is h the number of characters in the key code combination, decoder 26, burst counter 27, integrator 28, second element 29 OR, element NOT 30.

 The device receives information without prior clock synchronization, the reception of commands by this method is as follows. Input information is processed without reference to the fronts of the received elementary premises. Moreover, the time equal to the duration of one T symbol is divided into 3 equal intervals. During each interval, information from the output of the demodulator is integrated and at the end of the interval, the value of the received information is recorded: "0" or "1". Information recorded during the intervals of the same name is recorded in the corresponding memory blocks, where it is stored for the time required to receive telecommand commands. During T, the contents of each memory block, consisting of information symbols recorded sequentially at the same intervals, are alternately read and checked for compliance with the reference key combination and the encoding law. In (4), it was proved that during the time necessary to receive a command, at least one of the time intervals will be in the optimal reception zone.

 The device operates as follows.

 During the period of the reception frequency F (Fig. 2A), the frequency divider 21 generates at its outputs three sequences of short pulses 1, 2 and 3, offset from each other by 1/3 of the transmission duration of one T symbol (Fig. 2B). Pulse 2 (figb) information from the output of the integrator is recorded in the first shift register 18, delaying the received information by one period of frequency F.

 Pulse 3 (Fig. 2B) information from the output of the integrator is recorded in the second shift register 19, delaying the received information by two periods of frequency F.

 Pulse 1 (figb) information from the output of the integrator is copied to the first 1 block of memory and from the output of the first 18 and second 19 shift registers, the delayed information is copied to the second 2 and third 3 memory blocks.

 The sequence of pulses 1, 2, 3 through the second element OR 29 act on the installation input of the integrator 28 and translate it into its original state.

 Pulses 1 are set to the initial state of the burst counter 27.

 Thus at the first output of the decoder 26 is set to a logical signal "0". Thereby, the installation signal (Fig. 2G) is removed from the triggers 7-12 and through the element 30 the logic signal "1" is sent to the first element 23.

 Through the element And 23 the burst counter 27 receives pulses of frequency f> n + 1. The output code of the packet counter 27 enumerates addresses from zero to n memory blocks of the key code combination.

 In this case, the reference key code combination is read to the second inputs of the comparison elements 4-6. The signals at the output of the third circuit OR 20, as well as at the first and second outputs of the decoder 26 are shown in figv, D, D.

 The sequence of pulses 1, 2 and 3 (Fig. 2B) reads information from the output of the integrator either directly to the memory unit 1 or through the shift shift registers 18, 19 to the memory blocks 2 and 3.

 The formation of a packet of n + 1 pulses arriving at the input of the address counter 24 leads to updating at each clock cycle for one bit of information recorded in each of the memory blocks. The introduction of shift registers 18 and 19 provides a time spacing in the reception of information on different subchannels, i.e., makes it impossible to select a key code combination simultaneously on two or three subchannels. This allows for simultaneous parallel reading of information from three memory blocks and ensures the achievement of the goals of the invention — improving the speed of the device. The processing cycle of the information accumulated in the memory blocks begins with pulse 1, which unlocks the operation of the device.

 When pulse 1 writes the last character of the control command to one of the memory blocks 1, 2, or 3, the first of n pulses of the processing frequency f received through the OR circuit 20 to the input of the address counter 24 will read the corresponding memory from this memory block a comparison element 4-6 of the first character of the key codeword. At the same time, the same pulse from the output of the And 23 element switches the burst counter 27, which is the address counter for the memory block of the key code combination. In this case, the first character of the reference key combination is also read from the output of the memory block of the key code combination to the second input of the comparison circuit.

 Comparison of the received and reference symbols occurs on the comparison elements 4-6. If the characters do not match, the logical 1 signal appears on the output of the comparison element, which sets the RS-trigger of this subchannel to the logical 0 state on the output. After comparing all K symbols, the key (the counter of bursts 27 counts K pulses of frequency f), the decoder 26 generates a pulse at the second output (Fig.2D), which transcribes to the output of the D-flip-flops 10-12 the state established at that time on their D-inputs . If, on one of the subchannels, the accepted key combination coincides with the reference one, the logical “1” state will be set at the output of the D-trigger of this subchannel, which will allow the information part of the control command to pass through the And element of this subchannel (13-15) and the OR element 16 to the input shaper control signals 17. Due to the introduction of shift registers 18 and 19, it is impossible to simultaneously select the key on two or more subchannels.

 If the information read in block 17 corresponds to the encoding law, it is registered as a received telecontrol command.

Claims (1)

 A device for receiving telecommand commands containing an integrator whose output is the input of the device, the output is connected to the input of the first memory block, the reference frequency generator is connected to the input of the frequency divider, two OR elements, an AND element, an RS-trigger, a control signal generator, an address counter, pulse packet counter, memory blocks, the output of the first OR element is connected to a control signal generator, characterized in that, in order to increase the admissible reception rate, shift registers are introduced into the device, elements cf alarms, RS-flip-flops, D-flip-flops, OR elements and a group of AND elements, a key code combination memory block, a decoder, a NOT element, the first, second and third outputs of the frequency divider through the second OR element are connected to the control input of the integrator, the first output is connected directly to the control inputs of the first, second and third memory blocks, to the first input of the third OR element and to the installation input of the pulse packet counter, the second and third outputs are connected to the C-inputs of the first and second shift registers, respectively, the outputs to which are connected to the inputs of the second and third memory blocks, the D-inputs of the shift registers are connected to the integrator output, the output of each memory block is connected to the first inputs of the same comparison element and the same element AND groups, the outputs of the elements AND groups are connected to the inputs of the first OR element, the output of the third the OR element is connected through the address counter to the address inputs of the memory blocks, the outputs of the pulse packet counter through the memory block of the key code combination are connected to the second inputs of the comparison elements and directly to the inputs of the decoder, the first output of which is connected to the S-inputs of RS-flip-flops and the R-inputs of D-flip-flops and through the element NOT to the first input of the AND element, the second input of which is connected to the reference frequency generator, the output is connected to the second input of the third OR element and with the counting input of the pulse packet counter, the second decoder output is connected to the C-inputs of the D-flip-flops, the outputs of which are connected to the second inputs of the same elements AND groups, the outputs of the comparison elements are connected to the installation inputs of the same-name RS-triggers, the outputs of the RS-trigger s connected to the D-inputs of D-flip-flops of the same name.

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