SU1339876A1 - Apparatus for generating pulse trains - Google Patents

Abstract

The invention can be used to generate various combinations of code pulses in communication devices with pulse code modulation. The purpose of the invention is to increase the reliability of the device. The device contains a pulse count 4, a memory block 6, a control block 8, a pulse synchronization bus 1, a control pulse 2 and a start pulse 3, a driver 5 including D-flip-flop 13, an AND 14 element and inverters 15 and 16 and D -triggers 7.1-7.K, and the control unit 8 is designed as a pulse counter 10, a decoder 11 and a trigger 12. The introduction of these elements eliminates the need to use a comparator, the output of which can cause interference signals when changing codes at its inputs, 1 silt from S from 00 to 00 vi O5

Description

The invention relates to radio engineering and can be used to generate various combinations of code pulses in communication devices with pulse code modulation and in measuring devices.

The aim of the invention is to improve the reliability of the device.

The drawing shows the functional diagram of the device.

The device contains bus 1 for synchronization pulses, bus 2 for control pulses, bus 3 for a start pulse, pulse counter 4, driver 5, memory block 6 D-triggers 7.1 ... 7.K, control block 8, output buses 9.1 ... 9.K device In the control unit 8 includes a pulse counter 10 pulses, a decoder 11 and a trigger 12. In the shaper 5 includes a D-flip-flop 13, element AND NOT 14, inverters 15 and 16.

Bus 2 for control pulses is connected to the inputs of parallel recording D.1 ... D.I of the counter 10 of control block 8. Bus 3 is connected to the installation input JB unit trigger 12 of block 8. The installation input to zero of trigger 12 is connected to the output of the decoder 11, the inputs of which are connected to the outputs of memory block 6. The counting input of the counter 10 is connected to the overflow output of the counter 4, to which are also connected the D-input of the trigger 13 of the driver 5 and the C-inputs of the trigger 7.1., O7, k. The bit outputs of the counter 10 are connected to the address inputs A.1 .., A, 1-block 6 of the memory. The direct output of the trigger 12 is connected to the control input of the counter 10, the inverse output to the inputs to the zero setting of the counter 4 and the 7.1 trigger, .. 7.k. The bit outputs M, 1. ,, M.p of memory block 6 are connected to the inputs D.lo.D.n of parallel recording of counter 4, and the outputs M.nllo..MsP + k - to the inputs of D-flip-flops 7.1 ,. 7 k, the outputs of which are the output buses 9.1 .., 9.k devices.

Bus 1 for synchronization pulses is connected to the counting input of counter 4, the synchronization input of D-flip-flop 13 and through inverters 15 and .16 to one of the inputs of the AND-14 element, the second input of which is connected to the inverse output of flip-flop 13, and the output is connected to control input 4,

The device works as follows.

In the initial state, the trigger 12 is in the zero state, the control input of the counter 10 receives a zero-level signal, allowing it to record the number received on bus 2 in the form of a parallel binary code, and determining the address of the first of the group of memory cells of block 6 used to form a given pulse sequence. In all cells of memory block 6 in advance

written, based on the arrangements and durations of the pulses in the generated pulse sequences, binary numbers, with bits from 1 to n determine the arrangement and duration of the pulses, and bits from (n + 1) to (nk) are the distribution of pulses in k -the output of the device.

The signal level of the logical unit with the inverse output of the trigger 12,

I act on the inputs of setting the counter 4 to zero and trigger 7.1 ... 7, k, sets and maintains them in the zero state, prohibiting the counter switching by 4 pulses running on the bus 1. There are no signals on buses 9.1 ... 9. 9. No devices , since the 7.1 ... 7K triggers are set to the zero state.

Due to the fact that counter 4 is in the zero state, at its output overflow (zero) there is a logic zero level, if there is no synchronization pulse, and a signal of the level of logic one

in the presence of a synchronization pulse. The signal from the overflow output of counter 4 goes to. D-input trigger 13, the latter under the influence on its C-input synchronization pulses,

tumbling along bus 1 is set to the zero state.

The signal of the unit level from its inverse output enters the input of the element AND-HE 14, allowing the passage of double inverted sync pulses through it, which, entering the control input of the counter 4, do not change its zero state. From the overflow (zero) output

counter 4 pulses are also fed to the counting input of counter 0 and the synchronization inputs of C-flip-flops 7.1 ... 7.k. In this case, the counter 10 does not switch, since at its control input there is a logic level zero signal (from the output of the trigger 12), which determines the operation of the counter 10 in the parallel recording mode on the inputs D, 1 ... Dl, Triggers 7.1. ..7. Remain in the zero state, since their R input is fed to the zero signal (the level of the logical unit) from the inverse output of the trigger 12.

When a trigger pulse arrives at the bus 3 at the input to the installation of the trigger 12, it switches to the unit state, the signal preventing them from switching is removed from the installation input of the counter 4 and the inputs to the zero setting of the trigger 7.1 ... 7.k. At the control input of the counter 10, after the trigger 12 is switched, the logic unit level signal is set, enabling the counter 10 to operate in the counting mode. At the same time, the counter 10 maintains the state corresponding to the binary code recorded in it, which arrived on bus 2 until the start pulse arrived on bus 3.

When the next synchronization pulse arrives at the bus 1 by its termination, the output of the overflow (zeroing) of counter 4 (counter 4 is in the zero state) produces a logic zero level pulse, which is fed to the D input of the trigger 13 and to the trigger inputs of the 7.1 trigger. .7.K.

Zones are written in bits from 1 to p of the first cell from the group of memory cells used to form this pulse sequence. Therefore, the first received sync pulse on bus 1, which calls the zero level signal at the output of shaper 5 (element AND 14), received at the control input of counter 4, will confirm the zero state of counter 4 by rewriting the zeros of the first n bits of memory block 6 in counter 4. The binary number (spreading of zeros and ones) in the bits from (n + 1) to (n + k) words from block 6 determines whether there are 7.1.0.7. triggers on the D inputs for enabling them Te triggers 7.1 ... 7, k, to the D-BXO-codes of which from the outputs M, n + 1., M, n + k of block 6 signals of a single level are received, I turn on to and from their respective tires 9.1 ... 9.k begins to form the first pulse generirue9876

We are consistent. In the event that in the generated by the settlement unit there are not required the formation of a pulse at a given time (i.e., with a minimum delay), in all bits from (n + 1) to (n + k) words from block 6 are written zeros.

The signal from the output of the circuit and the reload of counter 4 also goes to

counting input; - counter 10 (on the difference from zero to one), switches it to the next state, which from the counter outputs of 10 in

5, the next address is sent to the address inputs of block 6, causing a new next word (binary number) at its outputs, the first n bits of which determine the temporal position of the next next (second) pulse in those of the generated sequences where it is present; the duration (the moment of the formation of the trailing edge) of the previous (first) pulse in those of the generated sequences, where the duration of the previous (first) pulse ended.

0 The last to bits of the word (binary number), coming from block 6, determine the outputs of the device, according to which the signals are output (if available in the discharge corresponding to the output, the value of logical 1)

C-i

The following (second after the start pulse) synchronization pulse, coming through bus 1, confirms the zero state of the trigger

d 13, since at its D-input there is a logical zero level. At the inverse output of the flip-flop 13, a logical one level is formed, which enters the input of the element AND-NO 14, allowing a sync pulse through the other input of the element AND-HE 14 through the inverters 15 and 16 to pass through. The output level of the logical zero NOT 14 posQ is blunt to the control input of counter 4, and the called binary number (the contents of the second memory location used to form this sequence) is in incremental order

The outputs M.1., M, n of the block 6 are fed to the one-by-one installation inputs D, 1 ,,, D, n of the counter 4. and the counter is set to the state corresponding to this number.

five

five

The next (third) trace of synchronization synchronization trigger 13 will be set to one.

Inverters 15 and 16 are used to delay the synchronization pulses by a time longer than the switching time of the flip-flop 13, in order to eliminate the appearance of interference pulses at the output of the AND-HE element 14.

Counter 4 counts incoming clock pulses. When overflow (zeroing) of counter 4 at its output of overflow (zeroing), a logical level zero momentum will be generated which, by its difference from zero to one (back front), will switch counter 10 and those of trigger 7.1 ... 7.k, to D- the inputs of which in the second, caused from block 6 memory of the word, there was a change of logical levels (t, e, replacing zeros with ones, or vice versa), i.e. the formation of the next pulse will begin in those of the sequences where it is located, and the formation of the first pulse in those sequences where the duration of the first pulse has formed is stopped.

 The temporal position of the generated pulse (or the duration of the generated pulse) corresponds to the number of states of counter 4 between the corresponding formed pulse (pulse front when forming the pulse duration) and the generated pulse (sp, pulse of pulse when forming the pulse duration).

If the temporal position between adjacent pulses (or pulse duration) in the simultaneously generated k sequences of pulses exceeds the number of states of counter 4, which is 2, then from. The cells of block 6 receive a word, the last to which bits, issued by the second group of outputs of block 6, contain zeros (or when forming the pulse duration - one),

At the same time, after counting by counter 4 to overflow (zeroing), an output is generated at the output of overflow (zero), which, since the D-inputs of all 7.1 o.7.k triggers are zeroes (during the formation of pulse durations, one) does not switch D-triggers

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7.1 ... 7.k and, therefore, switchings on the time code 9.1 .., 9.k.

The pulse from the overflow output g of the counter 4 switches the counter 10 to the next state for calling from the next word block 6, which can again determine either the temporary position (duration) and the distribution of the outputs of the generated pulses in the generated sequences, or part of the time interval between impulse themselves (pulse duration), i.e. pass issue

15 pulses in the interval between them are greater than the number of states of the counter 4, and also with the duration of the generated pulses greater than the number of states of the counter 4. V

In this case, the information in the bits from (n + 1) to () does not change and corresponds to the preceding word.

Thus, all pulses of the generated sequences are sequentially generated.

After the formation of the last pulse in the generated sequences of the memory block 6 is called (the address is generated in a similar way, i.e.

30 the next state of the counter 10)

The pre-selected and recorded binary number, which, arriving from the bit outputs of memory block 6 to the inputs of the decoder 11, is decoded at the last. For such a number, for example, the number 11.100..O will be chosen, where in the first n digits there is one, and in the last K digits there are zeros.

40 The signal from the output of the decoder 11 after decoding the number 11 ... 100.0 arrives at the input to the zero setting of the trigger 12, sets it to the initial state. The last signal 45 from its outputs resets counters 4 and 10, as well as triggers 7.1 .., 7.k.

The process of generating pulse sequences has ended and

50 device returned to its original state

Upon receipt of the control pulses and the start pulse on buses 2 and 3, the pulse forming processes are repeated, and if the control pulse combination on bus 2 has entered a new one, then the counter 10 is set to a new initial state. one

 N.OGO addresses, which makes it possible to form, using other cells of memory block 6, K sequences of pulses that are different from those generated during the previous cycle of operation.

An increase in the reliability of the proposed device as compared to the known one was achieved by eliminating the comparator from the functional circuit, the output of which can cause interference pulses when changing codes on its inputs, which leads to a distortion of the duration of the generated pulses.

Claims (1)

Invention Formula A device for generating pulse sequences containing a pulse counter, a memory unit and a control unit, the first output of which is connected to the installation input of a pulse counter, the counting input of which is connected to the synchronization pulse bus, the address inputs of the unit Editor L.Gratillo Compiled by Yu.Sibir to Tehred L. Serdyukova Proofreader E. Roshko Order 4245/55 Circulation 901 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 39876i the memories are connected in a corresponding way with the second outputs of the control unit, the first, second, and third inputs of the control unit are respectively connected to the trigger pulse bus, the control pulse bus, as well as to the memory block memory outputs, characterized in that 0 to ensure reliable operation, a driver and D triggers are entered into it, the synchronization inputs of which are the fourth input of the control unit and the first input of the driver 5 is connected to the output of a pulse counter, the bitwise inputs of which are respectively connected to the first group of bitwise outputs of the memory block, the control input of the meter is connected to The 2Q output of the former, the second input of which is connected to the bus of synchronization pulses, the second group of one-bit outputs of the memory unit, respectively, is connected to the D inputs of 1b-trig 25 gera, the setup inputs of which connected to the first output of the control unit.