SU1439744A1 - Device for shaping coded sequences - Google Patents

Abstract

The invention relates to computing and can be used in automatic data processing systems. The invention eliminates the effect of a limited cycle time of the device. on the frequency of formation of elements of code sequences, which increases the overall speed of the device. A device for generating code sequences contains a pulse generator 1, an AND element 2, a frequency divider 3, a delay element 4, three counters 5.10 and I3 pulses, a comparison element 6, two triggers 7 and 9, two formers 8 and 15 short pulses, three of memory element II, 14 and 21, demultiplexer 12, element 16 OR, register I7, two blocks 18 and 19 of the flip-flops (18.1, ..., 18.П and 19..,. "., 9.p), block 20 registers (20.1, ..., 20.p). 1 il. S WITH

Description

g

42 00

from 4

four

The invention relates to computing technology and can be used in automatic data processing systems.

The purpose of the invention is to increase the speed of the device.

The drawing shows a functional diagram of the device.

The device contains a pulse generator 1, an AND 2 element, a frequency divider 3, a delay element 4, a first counter 5 pulses, a comparison element 6, a first trigger T, a first driver 8 short pulses, a second trigger 9e a second counter 10 pulses, the first memory element 11 , demultiplexer 12, third pulse counter 1, second memory element 14, second shaper 15 short pulses, element OR 16, register 17, first 18 and second 19 blocks of triggers (18-1, .., 8-n) and (19-1, ..., 19-p), block 20 of registers (20-1 ,, .., 20-p) and the third memory element 21. In addition, the designated start inputs 22 and the initial installation 23 of the device and the outputs 24 of the device.

The device works as follows.

Before the device is started by a signal. The initial installation, which is fed to the input 23 of the initial installation of the device, is reset to 1 minute.

10 addresses, TV-triggers 18-1.0., 18-p

35

the first 1 8 and 1 9-1,.,., 19-p the second 1 9 trigger blocks, registers 20-, "., 20-p block 20 registers, is set in one state divider 3 frequency, counter 5 and counter 13 the addresses, Q and through the element OR 16 are also reset to zero the register 1 7 and the RS flip-flop 9.

The start pulse, which arrives at the input of the D-flip-flop installation 7, sets it in one state, allowing the pulses from the generator 1 output to pass through the AND 2 element to the counting input of the address 13 counter and the divider 3 frequency input. From the first and second outputs of the divider 3 frequency

50

square-wave sync signals are taken, measuring the actual clock cycles and half-steps of the device operation. Synchro signals from the first output of the divider 3 frequencies are fed to the input of the element 4 for-

the holder, from the output of which is fed to the counting input of counter 5, the first impulse from the output of delay element 4 translates counter 5 into the next, zero

0

five

Q

0

five

new state. Code from the counter outputs

5 arrives at the first input element

6 comparison.

The zero exit code of the address 10 counter is fed to the address input of the first memory element 1, which stores the numbers of ticks in which at least one of the outputs of the device 4 change.

At the zero address, memory element 11 reads the first code of the clock number. This code goes to the second input of comparing element 6, which reduces the code value by one low-order one and compares the result with counter code 5. If the compared codes match, the potential of logical O from the inverse output of comparing element 6 is fed to the control input of the demultiplexer 2 A single signal from the direct output of the comparison element 6 is fed to the first FS of the 8 short pulses. In this case, a short unit impulse is formed, which sets the RS flip-flop 9 into the unit state via the S input. The single signal from the direct output of the RS flip-flop 9 is input to the sampling inputs of the second 14 and third 21 memory elements, as well as to the input of the counting resolution of the address 13, which, by the action of the sync signals to its counting input, begins to change its state On the address inputs of the second 14 and third 21 memory elements I will form a sequence of address values.

In the second memory element 14, a sequence of code groups is stored. Each group of codes corresponds one-to-one to one code (clock number) from memory element 11 and contains channel number codes (device output numbers 24), which change their state in the corresponding device operation cycle. In the group, codes are listed in random order. The channel number code contains an extra bit, which in the last code of each group accepts a unit value and a zero value in other codes. This terminator of the group of codes is read from the control output of the second memory element 14.

The third memory element 21 stores two-bit switch codes that are mutually one-to-one

codes of groups of the second element 4 of the mi. The first (second) bits of the switching codes indicate by a single value the change in the output of the device in the first (second) half-cycle and in relation to the corresponding half-cycle of the preceding measure.

The channel number codes of the group that are read from the second memory element 14 are sent to the information inputs of the register 17, and its outputs to the address inputs of the demultiplexer 12, ensuring the sequential generation of single pulses at its outputs corresponding to the channel numbers of the group

From the first and second outputs of the third memory element 21, the first and second bits of the switching code, respectively, are input to the I inputs of TV-flip-flops 8-1, ..., 18-n of the first block 18 and TV-flip-flops 9-1 , .. 51 9-p of the second block 19, respectively (a single value at the V-input of a TV flip-flop allows changing its state to inverse with the arrival of a single pulse (front) at the T-input of a TV flip-flop). The T-inputs ix TV-flip-flops 18-i, 19-i of the first 18 and second 19 blocks (i 1, p) receive single pulses or a zero level from the ix outputs of the demultiplexer 12 Single pulses invert TV-triggers selected by V-entry. The signals from the outputs of the TV-flip-flops of the first 18 and second 19 blocks go to the first and second inputs of the corresponding registers 20-1 ,, ..,

0

five

0

five

0

five

group graduation. This signal is fed to the input of the second one, the driver 15 short pulses, from the output of which a short pulse is formed with a delay of t. comes through the OR element 16 to the reset input of the register 17 and to the R input of the RS flip-flop 9. At the same time, the register 17 and the RS flip-flop 9 are zeroed. The signal from the direct output of the RS flip-flop 9 stops changing the states of the address 13 and translates through the inputs of the second sample 14 and third 21 memory elements to the zero state. The signal from the inverted output of the RS flip-flop 9 transfers into the next state the address counter 10. In this case, the next clock number code is read from the first memory element I1.

The pulses from the output of the delay element 4 provide a counter with 5 real-time ticks and when the high bit of the counter 5 is set to a single value, the D-flip-flop 7 goes to the initial zero state, completing the operation of the device.

Claims (1)

Invention Formula A device for generating code sequences containing a pulse generator, the output of which is connected to the first input of the element I, the output of which is connected to the information input of a frequency divider, the first output of which through the delay element is connected to the counting input of the first pulse counter, 20-p block 20. The register register clock-40 second outputs of the first counter The ditch 20-1, ..., 20-p receives the synchronization signal from the second output of the 3 frequency divider, and the control inputs receive a signal from the output of the element 4 pulses are connected respectively to the first input of the comparison element and the installation input of the first trigger, the output of which is connected to the second delays, providing the input element I, the first formation, at zero value, receiving information, and at a single value, shifting it by one bit. As a result of receiving information at the output of register 20-i of block 20, the value of the signal received from you-gQ of the progress of the TV-trigger 19-i of the first block 1 19, and as a result of the shift - the value of the signal recorded in the register 20-i from the output of the TV-trigger 19-i of the second block 19. Simultaneously with the reading of the last group code, a single sign signal is read at the control output of the second memory element 14 a short pulse, the output of which is connected to the B input of the second trigger, the inverse output of which is connected to the counting input of the second pulse counter, the output of which is connected to the address input of the first memory element, the output of which is connected to the second input of the reference element whose output is connected to gg by the control input of the demultiplexer, the third pulse counter, the output of which is connected to the address input of the second memory element, the first output of which is connected to the input of the second pulses are connected respectively to the first input of the comparison element and the installation input of the first trigger, the output of which is connected to the second the input element And, the first form Short pulse pulse, the output of which is connected to the B input of the second trigger, the inverse output of which is connected to the counting input of the second pulse counter, the output of which is connected to the address input of the first memory element, the output of which is connected to the second input of the comparison element, the output of which is connected to the input control unit, the third pulse counter, the output of which is connected to the address input of the second memory element, the first output of which is connected to the input of the second the short pulse generator, whose output is connected to the first input of the OR element, the second output of the second memory element, and the output of the OR element are connected respectively to the information input and the input. reset register, the output of which is connected to the address input of the demultiplexer, the outputs of which are connected to the T input of the same trigger of the first trigger block, and the second trigger block j the synchronization input of the first trigger is the device start input, trigger trigger inputs; The first and second trigger blocks: 0 are connected to the second input of the OR element, with the installation inputs of the first. The second and third pulse counters and the frequency divider are the input of the initial installation of the device, characterized in that, in order to increase the speed of the device, a register unit is entered into it: the third memory element, the first and second outputs of which are connected to V -inputs triggers, respectively, the first and. second blocks triggers the direct output of the second trigger is connected to the sampling inputs of the second and third memory elements and the counting resolution input of the third pulse counter, the counting input of which is connected to the output of the AND element, the R input of the second trigger is connected to the output of the OR element, the direct output of the comparison element is connected with the input of the first short impulse generator, the address input of the third memory element is connected to the output of the third pulse counter, the outputs of the flip-flops of the first and second blocks of flip-flops are connected respectively with the first and second info The memory inputs of the same registers of the register block, the second output of the frequency divider is connected to the register synchronization inputs of the register block whose control inputs are connected to the output of the delay element, the register setup inputs of the register block are connected to the initial setup INPUT of the device, the output of the register block are device outputs.