SU1374430A1 - Frequency-to-code converter - Google Patents

Abstract

The invention relates to automation and measurement technology and can be used in digital process monitoring and control systems. The aim of the invention is to expand the scope by simultaneously generating output information on the last and previous periods of the measured frequency. The converter contains a pulse shaper, a trigger, a pulse generator, two pulse counters, two registers and six AND elements, which form two channels operating in series. When measuring the current period of the input frequency by counting the generator pulses in the first pulse counter, the code of the last converted period of the input frequency is stored in the second register, which corresponds to the second pulse counter and the second channel, while the code of the previous period is stored in the first register. Further, the process of converting the current period is repeated, but already in the counter of the parallel channel. 2 Il. f sh (L

Description

with

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ten

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11374430

The invention relates to automation and measurement technology and can be used in digital process monitoring and control systems.

The purpose of the invention is to expand the field of application by simultaneously generating output information about the last and previous periods of the measured frequency.

Fig. 1 shows a functional 1a diagram of the frequency converter in the code; 2, time diagrams of his work.

The frequency converter in the code (Fig. 1) contains a pulse former 1, a trigger 2, counters 3 and 4 pulses, registers 5 and 6 of memory, elements I 7-12, a generator 13 and j pulses, input bus 14, bus 15 and 16 output codes, output buses 17 and 18 of the period feature, reset bus 19, output synchronization bus 20.

The frequency converter in the code works as follows.

Suppose that in the initial position the counters 3 and 4, the registers 5 and 6 are in the zero state. This state can be established in the usual way when the power is turned on by the front of the supply voltage. Suppose, for definiteness, that the first input frequency pulse arriving at the input bus 20 at time t min

Where

20

25

thirty

- the minimum possible period of the process under study. Thus, when forming the code of the first period, the reset pulse passed during the counting of the counter 3, confirming the zero state of the counter 4 (FIG. 2d) through the AND 9 element, and through the And 11 element - the zero state of the register 5 (FIG. 2d),

During the second period, the logical unit from the inverse output of the trigger 2 maintains in the open state the element 10. As a result, the counter is filled with 4 pulses of the generator 13 (Fig. 2d). Before the end of the second period, an impulse passes to the reset bus 19, which, after elements 8 and 12, zeroed the counter 3 and register 6 (in this case, confirms the zero state of register 6), the second period ends with the arrival of the next (third) pulse 1, In this case, the trigger 2 returns to the one state, ensuring the transfer of information from the counter 4 to the register 6 (FIG. 2e).

Thus, at the end of the second period, the first period code will be present on tires 15 of the output code, and on the tires 16 of the output code, the code of the second period.

The process then repeats. Code

bus 14 (FIG. 2a), translates the third-period trigger-35

ger 2 to a single state. At the same time, an arbitrary initial state will lead to arbitrary values of only the first two periods, the number of tires 15, the fourth code on tires 16, and so on. To select the last of the terminated and the penultimate periods of the input frequency T 4 and T;

Noah bus 20 at time t min

Where

0

five

0

- the minimum possible period of the process under study. Thus, when forming the code of the first period, the reset pulse passed during the counting of the counter 3, confirming the zero state of the counter 4 (FIG. 2d) through the AND 9 element, and through the And 11 element - the zero state of the register 5 (FIG. 2d),

During the second period, the logical unit from the inverse output of the trigger 2 maintains in the open state the element 10. As a result, the counter is filled with 4 pulses of the generator 13 (Fig. 2d). Before the end of the second period, an impulse passes to the reset bus 19, which, after elements 8 and 12, zeroed the counter 3 and register 6 (in this case, confirms the zero state of register 6), the second period ends with the arrival of the next (third) pulse 1, In this case, the trigger 2 returns to the one state, ensuring the transfer of information from the counter 4 to the register 6 (FIG. 2e).

Thus, at the end of the second period, the first period code will be present on tires 15 of the output code, and on the tires 16 of the output code, the code of the second period.

The process then repeats. Code

on tires 15, the fourth code - on tires 16 and t, d. To select the last of the terminated and the penultimate periods of the input frequency T 4 and T;

the signal of the logical unit in pr - 40 uses output buses 17 and 18

The output of flip-flop 2 (FIG. 26) allows the pulse 13 of the generator 13 to pass to the counting input of counter 3, the filling of this counter will continue until the unit potential from trigger 2 disappears, t, e, until the first period (FIG. 2c). When a second pulse appears on the input bus 14, trigger 2 changes its state, forming at its inverse output a write pulse from the counter, 3 into register 5,

The reset pulses are sent to the reset bus 19 (FIG. 2j) from external devices, either after the processing of the information received from the frequency converter or the delay of the clock pulse from output 45

50

55

signs of the period.

The principle of the allocation of periods T; and T; it is convenient to follow the time diagrams of FIG. 2; Reading of information from buses 15 and 16 should be in the interval from the beginning of the next period (pulse on the output synchronization bus 20) to c6pqca (pulse on bus 19). if the counter is open (filled) in counter 3, then the period T. is recorded in register 6 and the code for period T is in register 5, thus, a logical one on the output bus 17 indicates the presence of a period code T on bus 15 ;, and a logical unit on the output bus- 18 indicates the presence of a period code on buses 16 ; .

five

0

five

signs of the period.

The principle of the allocation of periods T; and T; It is convenient to follow the time diagrams of FIG. 2. Information from tires 15 and 16 must be read in the interval from the beginning of the next period (pulse on the output synchronization bus 20) to c6pqca (pulse on the bus 19). It is seen from the time chart that if o. The counter 3 is open (filled), then the period T. is recorded in register 6 and the period code T. is in register 5, Thus, the logical one on the output bus 17 indicates the presence of the period code T on tires 15; a unit on the output bus- 18 indicates the presence of a code 16 on the tires Period T; .

Thus, the frequency converter in the code measures each period of a pulse sequence arriving at its input and, for most of the current period, keeps the last two and the second to last codes at the outputs.

Claims (1)

Invention Formula The frequency converter in the code containing the pulse generator, the first pulse counter, the first and second elements And, the first inputs of which are combined and connected to the forward output of the trigger, the third and fourth elements And, the first inputs of which are combined and connected to the inverse output of the trigger, and the second the inputs of the first and fourth elements And are combined, differing by the fact that, in order to expand the scope of application due to the simultaneous formation of the output information on the last and previous periods of the measured frequency, into it the second pulse counter, pulse generator, the fifth and sixth And elements and the first and second registers, outputs are entered 0 five 0 five which are respectively the first and second output code buses, information inputs are connected to the corresponding outputs of the first and second pulse counters, respectively, and the reset inputs are connected to the outputs of the fifth and sixth And elements, the first inputs of which are combined with the second inputs of the second and third And elements and are a reset bus, wherein the recording inputs of the first and second registers are respectively combined with the second inputs of the sixth and fifth elements And, and are connected to the inverse and forward output the trigger dam and are respectively the first and second output buses of the period feature, the output of the pulse generator is connected to the second input of the first element I, the trigger input is the output synchronization bus and connected to the output of the pulse driver, the input of which is the input bus, and the counting inputs .and the reset inputs of the first and second pulse counters, respectively, are connected to the outputs of the first, fourth, third and second elements And, qjus.l y d e f 3 Li t t -i t -t - / t LI Ix not.2