SU1368853A1 - Device for measuring time intervals - Google Patents

Abstract

The invention is intended to measure a random sequence of time intervals determined by the location of the pulses on the time axis. The device for measuring time intervals contains 1 clock pulse generator, switch 4, memory register 5, triggers 6.24, differentiation elements 8.9, inverter 10, input buses (III) 12,13,15,16, output Sch 14, OR elements NOT 19.20, elements OR 21.26. The invention extends the functionality of the device by providing for selection and measuring the durations adjacent to each other on the time axis of the time intervals. 1 il.

Description

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The invention relates to a pulse technique and is intended to measure a random sequence of time intervals determined by the arrangement of pulses on the time axis, and can be used in systems for analyzing the laws of the distribution of random signals.

The aim of the invention is to expand the functionality by providing selection and measuring durations adjacent to each other on the time axis of the time intervals,

The drawing shows a functional diagram of a device for measuring time intervals.

The device for measuring time intervals comprises a clock pulse generator 1, the first element AND 2, the first counter of 3 pulses, the switch 4, the memory register 5, the first trigger 6, the second element 7 and 7, the first differentiation element 8, the second differentiation element 9, the inverter 10 the second counter 11 pulses (reversible), the first input bus

12 devices, second input bus

13 devices, output bus 14 of the device, the third input bus 15 of the device, the fourth input bus 16 of the device, the third counter 17 pulses, the third element AND 18, the first element NLI-NOT 19 per m inputs, the second element OR-NOT 20 per m inputs , the first element OR 21, the fourth element And 22, the fifth element And 23, the second trigger 24, the fourth counter 25 pulses (reversible), the second element OR 26. The output of the generator 1 is connected to the first input of the element AND 2, the second input of which connected to the input of the second element 9, the output element And 2 connected to the first input of the counter 3 pulses, the output of register 5 is the output bus 14 of the device, the input bus 12 of the device is connected to the first input of the element

And 7, the output of which is connected to the first input of the pulse counter 11, the output of the generator 1 is connected to the first input of the element 18, the third input of which is connected to the first input of the element 22, the third input of the element 2 and connected to the output of the trigger 6, the second the input of the counter 3 is connected to the second input of the OR element 26 and is connected to the output of the element 9, the n discharge outputs of the counter 3 are connected to the first group n of the inputs of the switch 4, the control input of the switch 4 is connected to the second input of the And 2 element, the second input of the And 7 element and connected to the first output tr Iger 24, the second group p of the inputs of the switch 4 is connected respectively to the discharge outputs of the counter 17, the output of the switch 4 is connected respectively to the discharge inputs of the register 5, the first input of the trigger 6 is connected to the first input of the trigger 24 and the output of the inverter 10, whose input is connected to the third input element 23 and is the second input bus 13 of the device, the second input of the trigger 6 is connected to the second input of the element OR 21 and the output of the element OR NOT 20, the output of the first element 8 is connected to the second input of the pulse counter 17 and the first input nta OR 26, the output of which is connected to the synchronizing input of the register 5, the first input of the pulse counter 11 is connected to the first input of the pulse counter 25, the second input of the pulse counter II is connected to the output of the element And 22 the second input of which is connected to the second input of the pulse counter 25 and the output of the element And 23, the first input of which is connected to the first input of the element AND 7, n bits of the counter 11 pulses are connected respectively to the inputs of the element OR NOT 19, the first input of the counter 17 is connected to the output of the element AND 18, the inputs of the element OR NOT 20 are connected with the discharge outputs of the counter 25, the input of the first element 8 is connected to the second input

element And 18 and the second input element And 23 and is connected to the second output of the trigger 24, the second input of which is connected to the output of the element OR 21, the first input of which is connected to the output of the element OR NOT 19.

The device works as follows.

In the initial state, the triggers 6 and 24, register 5, counters 3 and 17 are reset. The counting inputs of the counters 3 and 17 pulses are not received, because the elements And 2, 18 and 22 are closed by a low potential from a single output of trigger 6. A low potential from a single output of trigger 24 with a counting input is closed element And 7, and a high potential from zero you -

the trigger 24 is prepared for opening element 23. In counter 25, bus 16 carries a binary code (the smallest code is one), corresponding to the pulse number of the input sequence, which determines the starting time of the time intervals - the starting pulse. A counter code corresponding to the stop pulse of the input sequence is entered into the counter II via the bus 15. The binary code corresponding to the stop pulse, entered in I1, is defined as the difference between the numbers of the stop and start pulses. Counters 11 and 25 are reversible, with the arrival of counting pulses from the output of element And 7, the content of counter 11 decreases by one for each counting pulse, and the contents of counter 23 increases by one. When the counting pulses from the output of the element 23 to the input of the counter 25, its content decreases by one for each pulse, and the content of the counter 11 increases by one unit when the counting pulses from the output of the element 23 through the element 22 to the input of the counter 11. The potential from the unit the output of the trigger 24 controls the switch 4. With a single state of the trigger 24, a high potential at the single output, the output outputs of the switch 4 switch the discharge outputs of the counter 17. With the zero state of the trigger 24, the output of the switch to mmutiruyuts The discharge outlets of the counter 3.

The Start signal on bus 13 opens an AND 23 element and the input sequence pulses pass to the input of counter 25. On an input pulse with a given number, the counter 25 is bent, and a positive impulse appears at the output of the OR-NOT 20 element, which through the element OR 21 enters the counting input of flip-flop 24, while a high potential appears at its single output. On the leading edge of the pulse from the single output of the trigger 24, the counter 3 is zeroed through the element 9. The clock pulse, the duration of which is longer than the response time of the switch 4, is used to rewrite the contents of the counter 17 through the output of the OR 26 element.

g 5 5 about 0

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five

switch 4 to register 5. In this cycle of operation, counter 17 is zeroed, therefore, register 5 remains in its zero state, i.e. The time interval measurement in this cycle is not performed. The high potential from a single trigger output 24 opens elements And 2 and 7.

The pulses from the output of the generator I pass through the element AND 2 to the input of the counter -3, which summarizes the number of incoming pulses. Through the AND 7 element, the input sequence pulses arrive at the inputs of counters 11 and 25. At the moment of counter zero resetting, the contents of counter 25 are equal to the value set initially in counter 11, at the output of the OR-NOT 19 element, a positive impulse appears through the element OR 21 sets trigger 24 to the opposite state — a high potential is set at zero output of trigger 24. Elements 2 and 7 are closed. On the counter 3, the number of pulses is fixed, which is proportional to the duration of the measured interval. On the positive front of the zero output of the trigger 24, through the element 8, the counter 17 is zeroed, thereby preparing it for counting when measuring the next time interval. The pulse from the output of element 8 through the element OR 26 into register 5 transfers the contents of counter 3 through switch 4. Information from register 5 is output to an arithmetic unit (not shown) for further processing. The high potential from the zero output of the trigger 24 opens the elements And 18 and 23.

Through the open element And 18 pulses from the output of the generator 1 is fed to the input of the counter 17, which summarizes the number of incoming pulses. The pulses of the input sequence come through the open element AND 23 to the input of the counter 25, which in this cycle performs subtraction, and through the open element And 22 to the input of the counter I1, which in this cycle performs their summation. At the moment of zeroing the counter 25, a positive pulse from the output of the element OR NOT 20 through the element OR 21 translates the trigger 24 into one state, the element I 18 is closed, and on the counter 17 fixes with a code proportional to the interval duration.

On the leading edge of the single output of the trigger 24, the counter 9 is reset by the element 3, and the synchronizing pulse from the output of the OR 26 element to the register 5 through the switch 4 is rewritten the contents of the counter 17 - the measurement result in this cycle. At a high potential, the AND 2 and 7 elements are opened from the single output of the trigger 24, the measurement of the next time interval begins with the help of the counter 3. The AND 23 element is closed by a low potential from the zero output of the trigger 24. Through the open element And 2, the pulses from the generator arrive at the input of the counter 3 , and through the open element And 7 the pulses of the input sequence arrive at the inputs of counters 11 and 25. The indicated cycle repeats. Counter I zeroed in on the pulse of the input sequence. By resetting the Start signal is reset — triggers 6 and 24 are reset to zero and elements 2, 1B, 7 and 23 are closed, all counters stop recalculating, and the contents of register 5 remain unchanged.

Claims (1)

Invention Formula A device for measuring time intervals containing a clock pulse generator, a first And element, a first pulse counter, a switch, a memory register, a trigger, a second And element, a first differentiation element, a second pulse counter, a second differentiation element, an inverter, a clock pulse output connected with the first input of the first element I, the second input of which is connected to the input of the second differentiation element, the output of the first element I connected to the first input of the first pulse counter, the output register the memory is connected to the output bus, the first input bus of the device is connected to the second input of the second element I, the output of which is connected to the first input of the second pulse counter, characterized in that, in order to expand its functionality, a third pulse counter is entered into it, the third the element And, the first and second five 0 five a second OR-NOT element, the first OR element, the fourth AND element, the fifth AND element, the second trigger, the fourth pulse counter, the second OR element, the output of the clock generator connected to the first input of the third And element, the third input of which is connected to the first input the fourth element And the third input of the first element And the output of the first trigger, the second input of the first pulse counter is connected to the second input of the second OR element and the output of the second differentiation element, n bit outputs of the first counter The first control input of the switch is connected to the second input of the first element AND, the second input of the second element AND and the first output of the second trigger, the second group of input n of the switch is connected to the third discharge counter of the third counter, the output of the switch is respectively connected with the bit inputs of the memory register, the first input of the first trigger is connected to the first input of the second trigger and the output of the inverter, the input of which is connected to the third input of the fifth element AND, the second input of the first the first trigger is connected to the second input of the first element OR and the output of the second element OR NOT; the output of the first differentiation element is connected to the second input of the third pulse counter and the first input of the second OR element, the output of which is connected to the synchronization input of the memory register, the first input of the second counter pulses connected to the first input of the fourth pulse counter, the second input of the second pulse counter connected to the output of the fourth element And the second input of which is connected to the second input of the fourth counter and pulses and an output of the first element And, the first input of which is connected to the first input of the second element And, n the output bits of the second pulse counter are connected respectively to the inputs of the first element OR NOT, the first input of the third counter is connected to the output of the third element And, the inputs of the second the element OR is NOT connected to the n bit outputs of the fourth counter, the input of the first differentiation element 0 five ABOUT five 1368853 keys to the second input of the third element with the output of the first element OR, ment, the second input of the first element whose first input is connected AND and to the second output of the second trigger with the output of the first element of the ILIGER, the second input of which is NOT connected.