SU1251152A1 - System for transmission of chronometric information - Google Patents

Abstract

The invention relates to the field of telemechanics and can be used to transmit time signals to the secondary clock over the existing telephone lines. The purpose of the invention is to increase throughput. For this purpose, when changing the sign in one of the bits of the primary clock, the chronometric information about the current time is transmitted in the serial code. Each of the significant digits is transmitted by a quasi-periodic address signal that indicates the unit of measure (minutes, tens of minutes, etc.), and a quasi-periodic information signal, the number of periods of which is equal to the significant digit. At the receiving side, the address and information signals are allocated by the corresponding selector, and by sequentially writing down the received significant digits, the serial code is converted into a corresponding register in parallel, which is displayed on the display unit. 1 hp f-ly, 4 ill. (Lu sd ate yu

Description

The invention relates to telemechanics and can be used for transmitting time signals to a secondary clock over existing telephone lines.

The purpose of the invention is to increase throughput.

FIG. 1 is a functional diagram of the transmitting side of the system; in fig. 2 - time diagrams of the formation of signals; in fig. 3 is a functional diagram of the receiving side of the system; in fig. 4 is a functional diagram of a sign change detector.

The system contains on the transmitting side primary clock 1, element 2 AND, valve 3, trigger 4, driver 5 of a quasi-periodic signal, group 6 of registers, detectors 7 sign changes, group 8 of triggers, groups of elements AND 9 and 10, element OR AND, register 12 , the converter 13 parallel code to serial; the distributor 3 contains the generator 14, the element OR 15, the decoder 16, the counters 17 and 18.

The system on each receiving side contains selectors 19 and 20, registers 21, display unit 22, counters 23 and 24, delay elements 25 and 26, And 27 elements. Each sign changing detector 7 contains a comparison unit 28, counter 29, inverter 30 and bus 31 clock pulses.

The system works as follows.

In the absence of alternating signs at the inputs of the detectors 7, the signals at their outputs correspond to a logical zero, the triggers 8 are in the zero state and prohibit the passage of information read pulses from the decoder 16 through the AND 9 elements. From the outputs of the AND 9 elements no readout pulses are sent to the second inputs registers 6. At the same time the absence of single signals at the inputs of the element OR 11 leads to a zero signal at its output, which prohibits the counting of clock pulses from the generator 14 by the counter 17 and resolves through the element IL And 15 is the counting of clock pulses from generator 14 in counter 18. At the output of decipher 16, alternating pulses of the primary clock are generated alternately.

Since there are no zero signals at the outputs of counter 12, there are no signals at the output of the converter 13 of the parallel code to serial, the quasi-periodic signal shaper 5 is in the idle mode, no signals are transmitted to the line. When the alternating signs appear at the outputs of the primary clock 1, single signals are generated at the outputs of the respective detectors 7, which causes the corresponding triggers of group 8 to be set to one.

The diagram (Fig. 2) shows an example of changing the code at the outputs of the primary minutes

hours from XX hours. 49 minutes to XX hours 50 minutes. At the time of the appearance of a single signal at the first output of the decoder 16, this signal coincides with a single

signal at the second input of the first element And 9 groups. A single signal is generated at its output, allowing information signals from the minute outputs of the primary clock 1 to the inputs of the converter 13. At the same time, the OR 10 and 13 elements block the counting in counter 18 and allow the counting in counter 17. At the output of meter 17, read pulses are generated and to the converter 19. At the output of the converter 13 is formed

the number of pulses equal to the code value on the minute outputs of the primary hours 1 (in the diagram of FIG. 2, zero minutes). Counter 12 has 15 states and outputs: 1 through 9, for transmitting information signals, which are the first outputs of the distributor 3; 10 — switching to trigger one state 4; from 11 to 14 - for the transmission of address signals; 15 - to switch the trigger 4 to the zero state, in addition, in this state, the counter 17

is found at the signal to prohibit the account at its control input.

After the parallel code is converted into a number-pulse (in states 1 through 9 of counter 17), a switching signal is triggered to a single state of flip-flop 4, a single signal from the output of flip-flop 4 coincides in an element with a single signal from an output of an OR 10 element. the enable signal is transmitted to transmit the address code through register 12 to the converter 13 (00 is the address code

minutes, 01 - ten minutes, 10 - hours, 11 - ten hours). At the same time, a single signal from the output of the trigger 4 provides an inversion of the quasi-periodic signal at the output of the driver 5 when transmitting the address signals. The transmission of address signals in the states 11-14 of the counter 17 is provided with a number-pulse code: 1 pulse - minutes, 2 pulses - 10 minutes, 3 pulses - hours, 4 pulses - 10 hours. When the counter 17 goes from 14

to state 15, the trigger 4 is reset to zero from the output 15 of the counter 12. Simultaneously from the same output, a single signal is fed to the inputs of the AND 10 elements and the resolution is enabled (through the OR 15 element) in the counter 18, due to

which counter 18 changes the state by one and ensures the shaping of the signal at the output of the decoder 16.

A single signal at the first inputs of the elements And 10 coincides with one of the signals

arriving at the second inputs of the elements And 10, and provides a reset of one of the triggers 8 (in this case, the first of the group), thereby removing the signal at the output

the first trigger 8 of group 10, but the signal at the output of the second trigger 8 of group 8, formed when changing numbers from 4 to 5 at the outputs of ten minutes of the primary clock 1, remains. Due to this, the control input of the counter 17 stores the signal allowing the counting ( from the output of the element OR 11) and the counter goes to state 1, then 2, etc., ensuring the conversion and transmission of information and address signals of tens of minutes in the converter 13. The corresponding register in the groups is opened with a pulse from the output of the second element And 9 (in a group on the f 2a, b, s show the signals at the outputs of the decoder 16, in Fig. 2e, g, s, and - the signals at the first inputs of the converter 13, in Fig. 2 k, l - the signals at the outputs of the counter 17 and the trigger 4; Fig. 2l "- signal at the input of the communication line). FIG. 2g shows how with code 0101, corresponding to 5, five periods of a quasi-periodic signal in state 1-5 of counter 17 are transmitted to the line.

The address of the tens of minutes in the form of two periods, opposite to the phase of the information signals, is transmitted to the 11 and 12 states of the counter due to the switching of the trigger 4 to the single state and the inversion of the signals generated in the former 5 by the signal.

When the counter 17 goes to the 15 state, the flip-flop 4 is reset to the zero state, the flip-flop 8, which generated the signal, is also reset to zero and the output signal of the OR element goes to zero. As a result, the count of the counter 17 is blocked and the element OR 5 of the counter 18, and the subsequent signals at the output of the decimator 16 begin to form with the oscillation period of the generator 14. Information on the line is not transmitted until the sign changes at least in one of the groups of outputs of the primary clock 1. Detector 7 can be implemented of the diagram of FIG. 4 using a comparison unit 28 and a counter 29. A code with states ranging from 0000 to 1001 from the outputs of the corresponding discharge of the primary clock is supplied to the second outputs of the block 28, and a code from the outputs of the counter 29 to the first inputs.

If the codes are equal, then at the output А-В of the block 28 is high, at the output of the inverter 30 - a low level, which prohibits the change of the counter 29 state. the signal at the output of the inverter 30 goes into one state, by setting the corresponding trigger of group 8 to one state.

0

five

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five

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five

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Simultaneously, the counting of the clock frequency pulses applied to the first input of the counter from the clock bus 31 is enabled, for which you can use the output of the generator 14 located in the distributor 3. The counting direction in the counter 29 is determined by the ratio of the codes on the first and second inputs of the block 28 If the shoe A at the first input is less than the code B at the second input of block 28, then at its first output, at the second input of the counter 29, a high level and the code value at the output of the counter increases with a clock frequency. Upon reaching equality of the codes A and B, the change in the state of the counter 29 is prohibited and the output signal of the detector 7 goes to the zero state. At the receiving side, the signal from the communication line is fed to the inputs of the selectors 19 and 20, each of which selects information and address signals, respectively. When receiving the address signals "Minutes," 10 minutes, "Hours," 10 hours, single signals are generated at one of the outputs of the counter 23. The delay time of the element 25 is 4.1-4.8 periods of the clock pulses of the generator 1. Due to this, the single the signal at the inputs of the elements And 27 from the output of the element 25 through Wits after the end of the counting of address pulses in the counter 23.

Thus, after the counting of the address pulses, a single signal can appear only at the output of one of the elements AND 27. The output of each element 27 is connected to the second input of the corresponding register 21. For example, when transmitting the minutes code, the output of the selector 20 selects one address pulse a single signal is valid from the first output of the counter 25; This signal records the minutes code from the outputs of the counter 24 to the register 21, to the second input of which the minutes indicator is connected. The delay element 26 delays the signal from the output of element 25 by the time the code from the output of counter 24 is written to register 26. From the output of element 29, counters 24 and 23 are reset to zero to ensure that they are ready to receive signals of the next bit.

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Claims (2)

1. A system for transmitting chronometric information containing a primary clock on the transmitting side, a parallel code-to-serial code converter, a quasi-periodic shaper, a trigger, on each receiving side a first selector, the output of which is connected to the first inputs of the first counter and the first delay element, display unit , the output of a quasi-periodic signal generator at the transmitting side is connected via a communication line to the input of the first selector at each receiving side, characterized in that In order to increase capacity, the sign change detectors, the first and second AND groups, the trigger group, the register group, the AND element, the register, the OR element, and the pulse distributor, each group of outputs of the primary clock, are connected to the system on the transmitting side. the sign and with the first inputs of the corresponding register of the group, the corresponding outputs of the register and registers of the group are combined and connected to the first inputs of the parallel code converter into the serial The output of each change detector is connected to the first input of the corresponding group trigger, the output of which is connected to the first input of the corresponding element AND of the first group and to the inputs of the element OR, which is connected to the first input of a quasi-periodic signal generator. to the input of the pulse distributor, the first outputs of which are connected to the second inputs of the parallel code to serial converter, to the third inputs of which the second outputs are connected the pulse distributor, the first of which is connected to the first trigger input, the last of the second outputs of the pulse distributor is connected to the first inputs of the second group elements and to the second trigger input, the output of which is connected to the second input of the quasiperiodic signal generator and to the second input of the And element, whose output connected to the first input of the register, with the second inputs of which connect Foam third outputs of the pulse distributor, the fourth outputs of which are connected to the second inputs of the corresponding elements of the first group and the second group, the outputs of the last of which are connected to the second inputs of the corresponding group triggers, the output of each element And the first group is connected to the second input of the corresponding group register, on each A second selector, a second counter, a second delay element, And elements and registers are introduced to the receiving side, the output of the communication line is connected to the first input of the second with the second selector of the meter, each output of which is connected to the corresponding 5 first inputs of registers, the outputs of which are connected to the inputs of the display unit, the output of the first delay element is connected to the first inputs of the And elements and to the input of the second delay element whose output is connected to the second inputs of the second and first counters The outputs of the last of which are connected to the second inputs of the corresponding And elements, the outputs of which are connected to the second inputs of the respective registers. five 2. The system of claim 1, wherein that the sign change detector contains a comparison unit, a counter, an inverter and a clock pulse bus connected to the first counter input, the outputs of which are connected to the first inputs of the comparison block, the first output of which is connected to the second input of the counter, the sign changing detector input is connected to the second block input comparison, the second output of which through the inverter is connected to the third input of the counter and to the output of the detector of the sign change. 0 With f7epSi / t / x f / cfcoS Have (