SU640284A1 - Command information receiving device - Google Patents

Description

the first input of the partial information analysis block, the second input of which is connected to the register output, the output of the third element OR is connected to the single input of the second trigger, zero output 5 of which is connected to the input of the delay element via the second element AND, the counter output is connected to the second input of the second switch and the first input of the mode selector, the second input of which is connected to the second output of the control unit, the input of which is connected to the first output of the partial information analysis unit and the zero input second about the trigger, the second input of the first element OR is connected to the 15th second output of the partial information analysis unit, the third output of which is connected to the third inputs of the second switch and the mode selection unit, the first output of which is connected to the unit 20 input of the first trigger, the second input of the third OR element and the second output of the mode selection unit is connected to the first output of the device, the output of the second switch is connected to the second output of the device, and 25 in that, the block of analysis of partial information sampling contains an encoder, a decoder, a register, a counter, three delay elements, four AND elements and an OR element, with the input of the first delay element 30 connected to the first inputs of the block and the first AND element whose output is connected to the first output of the block, the inputs of the second and third And elements and through the second delay element with the input of the counter, the encoder outputs 35 through the second and third elements AND are connected to the inputs of the register and through the element OR to the second input of the first element AND and the input of the fourth element AND, the output of which is connected through serially 40 connected meters and desh frator soediyen to a third input of the first AND gate, the first delay element output coupled to an input of the fourth AND gate and via a third delay member 45 with the second output unit, a second input and third output are connected respectively to the input of the encoder and the output register. The block diagram of the device is shown in FIG. 1. The block diagram of the analysis block 50 of a partial sample of information is shown in FIG. 2. The device for receiving command information contains a control block 1, a synchronization block 2, a mode selection block 3, a partial information analysis block 4, counter 5, triggers 6, 7, switches 8, 9, elements 10, ... 13, elements OR 14 ... 16, register 17, element 18 of delay and distributor 19.60 The unit 4 for analyzing partial data sampling contains register 20, counter 21, encoder 22, elements AND 23 ... 26, element OR 27, elements 28. .. 30 delays, decoder 31. 65 The device operates as follows. At the input of the device receives a sequence of commands. The information contained in each command is encoded, firstly, by the number of the command in the sequence and, secondly, by the type of parcel with which the command is transmitted. (A parcel is a sequence of pulses of the same shape. The number of types of parcels is determined by the number of pulses used). The number of pulses of the same shape in the parcel is selected depending on the level of interference in the communication channel. Before the start of operation, the trigger 7 is set to one, and the trigger 6 and the memory elements contained in the control unit 1, the synchronization unit 2. mode selection unit 3, counters 5 and 21, switch 8, registers 17 and 20 are set to zero (the setting circuit of the memory elements is not shown in Fig. 1 and Fig. 2). The operation of the device starts from the moment of arrival of the sending pulses to the second input of the synchronization unit 2, which serves to assign the incoming pulses to the internal frequency. From the output of block 2 synchronization pulses arrive at the input of the distributor 19, which serves to analyze the shape of the input signal. Depending on the shape of the input signal, the distributor 19 generates pulses at the corresponding outputs. So, for example, when a negative polarity pulse arrives at the input of the distributor 19, the pulses appear only at the first output. In the case of receiving a parcel consisting of rectangular positive pulses, impulses appear on both outputs of the distributor 19 (information pulses on the second output, and sync pulses on the first). The sync pulses through the OR 15 element arrive at the input of the switch 8, which serves to count the number of pulses entering the device and control the recording of information in the register 17. When the first sync pulse arrives, the switch 8 generates a signal that opens the And 13 element and the first information pulse generated at the second output of the distributor 19, is recorded in the first bit of the register 17. When the second clock pulse arrives, the element And 13 is triggered so that the second information pulse is recorded In the second register bit 17. In the same way, the following pulses of the parcel arriving at the input of the device are written into the register 17. The information contained in register 17 enters block 4 of analyzing a partial sample of information at the input of encoder 22. In the case of receiving a parcel consisting of positive rectangular pulses, in all bits of register 17 will be recorded "units, and encoder 22 will form the signal at one of the outputs, which through the element OR 27 opens the elements AND 26 and AND 23.

After receiving, for example, the ninth clock pulse, the switch 8 generates a signal which, through the element 12, enters the block 4 at the input of the element 28 of the delay. This signal triggers element 26 and the counter 21 is set to the first position. Each position of the counter 21 corresponds to the reception of eight identical pulses of one parcel. After the information is written to the counter 21, the output of the delay element 30 is a signal that, through the OR element 14, sets the switch 8 and the register 17 to the initial state, preparing the device to receive the next eight sending pulses. The next eight pulses of the transmission are received in the same way as described above, after which the counter 21 is set to the next, second position. After receiving a predetermined number of sequences of eight identical pulses, a signal appears at the output of the decoder 31, which opens element AND 23. At the next signal arriving at the first input of block 4, element 23 triggers, the output of which polls elements AND 24 and 25. Depending on the signals at the outputs of the encoder 22, either the element AND 24 or the element 25 is triggered and the sign of the received command is written to register 20.

In addition, the signal from the output of the AND element 23 sets the trigger 7 to a bullet state, as a result of which the reception of the following (redundant) burst pulses is prohibited. At the same time, the same signal is fed to the input of control unit 1, which, after the time required for the excess pulses to complete, generates a signal arriving at block 3. Depending on the command number in the sequence coming from the output of counter 5, and the sign of the received command, the block 3 generates one of two control signals that determine the further operation of the device: either receiving the next command or issuing messages.

If it is necessary to receive the next command, then block 3 generates a control signal at the second output. This signal through the third element OR 16 sets the trigger 7 into the unit state, thus preparing the device for receiving the next command. If a signal appears at the first output of block 3, the device starts to issue a message. This signal triggers a trigger 6, the output of which goes to switch 9 and opens element 10. Switch 9, depending on the command number in the sequence coming from the output of counter 5, and the sign of the message coming from the output of block 4, begins to form a message. The duration of the message is formed by the trigger 6 and the switch 8 as follows. Through the open element And 10 from the first

the output of the control unit 1 pulses arrive at the second input of the switch 8. After counting the required number of pulses, the switch 8 generates a signal that sets the triggers 6 and 7 and the switch 8 to the initial state.

As a result, the device finishes issuing the message and prepares to receive the next command. Simultaneously, the signal from the output element

18 delay enters the counter 5, which remembers the number of messages issued and generates the output number of the next command.

In the case of receiving a package consisting of

square negative pulses, the recording of information pulses in the register 17 is not made. After receiving eight sending pulses, the information control is checked in register 17 and the corresponding sign is written to register 20. Depending on the number of the command in the sequence and the indication of the command, the switch 9 issues a corresponding message.

When using this invention, a reliable reception of command information is provided with a high level of interference in the communication channel due to the organization of multiple reception of one message and suppression of the interference signal. In addition, the device provides the formation of messages of the required duration and corresponding to various commands, which are transmitted using physically identical

parcels

Claims (1)

1. A device for receiving command information, comprising a control unit, synchronization unit, first switch, two triggers, counter, OR element, register, four AND elements, with the first output of the control unit connected to the first inputs of the first AND element and the block synchronization, the output of the first element OR is connected to the first inputs of the register and the first switch, the outputs of which are connected to the first inputs of the second, third and fourth elements respectively, the output of which is connected to the second input of the register, the second input of the synchronization unit is connected to the input of the device, that, in order to increase the reliability of reception, a distributor, a selection unit