SU1688438A1 - Data transceiver - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase throughput. The device contains a clock generator 1. amplifier 2. low pass filter 3, shaper 4 rectangular pulses, counters 5, 9 and 26, decoders 6, 10 and 27, shapers 7 and 24 short pulses, blocks 8, 13, 14 and 19 delays, triggers 11 and 12, registers 15 and 21, buffer register 16, information consumer block 17, RS flip-flop 18, information source 20, frequency divider 22, multiplexer 23, AND 25 element, D-flip-flop 28 and OR 29 element. The RS flip-flop 18 synchronization pulse in the device is generated only when the next data from the source 20 does not evayut come into register 21 during the formation of the first pulse pause T1 series. The synchronization of the synchronization pulse shaper is possible only with the first pulse of the T1 series, which ensures the correct formation of the information pulse. The absence of a synchronization pulse between the fields provides an increase in the capacity of the device. 1 silt, fe Ov 00 with co 00

Description

The invention relates to radio engineering and can be used for serial transmission of digital data in duplex mode.

The purpose of the invention is to increase throughput.

The drawing shows a structural electrical circuit of the proposed device.

The device contains a clock oscillator 1, amplifier 2, low-pass filter 3, shaper 4 rectangular pulses, first counter 5. first decoder 6, first shaper 7 short pulses, first delay block 8, second counter 9, second decoder 10, first 11 and second 12 triggers, second 13 and third 14 delay blocks, first shift register 15, buffer register 16, information consumer block 17, RS flip-flop 18. fourth delay block 19, information source 20, second shift register 21, frequency divider 22 multiplexer 23, the second driver 24 orotkih pulses, AND gate 25, a third counter 26, a third decoder 27, D- flip-flop 28, an OR gate 29.

The device works as follows.

The divider 22 divides the input frequency from the clock generator 1 and generates at its three outputs three series of pulses i T1, T2, TZ of different duration, arriving at the inputs of the multiplexer 23. The selection of a series of pulses and their duration at the output of the multiplexer 23 depends on the control signal entrances. Using shaper 24 (differentiating chain) on the trailing edge of each pulse, the KS flip-flop 18 and counters of the divider 22 are reset to obtain pulses with a duty cycle of 1/2. The data from source 20 is entered by a parallel code in shift register 21. The data tracking strobe sets the counter to zero. The front of the next pulse of the T1 series from the first output of the splitter 22 frequency trigger 18 is set to 1 Another leading edge of the pulse from the output of the RS flip-flop 18. which is delayed by the pulse pause time And from the end of the cycle forming the last pulse at the output of the multiplexer 23. The D-flip-flop 28 is set to the enable state through the element 25 and performing a shift in the register 21 and counting the number of transmitted bits by the counter 26. Furthermore, at the control input ultipleksora set value signal 23, providing formation of pulses T1 and T2 depending on the value of the output signal to the register 21. After the data are transferred all bits in the counter 26 ustanovits code. equal to the number of transmitted bits, and at the output of the decoder 27, Vits readiness signal for transmission of the next field of data to the source 20. With this signal, D-trigger 28 is set to the state ensuring the formation of multiplexer 23 pulses of synchronization duration TZ.

Due to the RS flip-flop 18, a synchronization pulse in the device is generated only when the next data from the information source 20 did not have time to go to the shift register 21 during the pause time of the first T1 pulse. The interruption of the synchronization pulse formation is possible only by the first pulse of the T1 series, which ensures

0 correctness of the formation of an information pulse. The absence of a synchronization pulse between the fields increases the capacity of the device. At the same time synchronization of transmitter counters

5 and the receiver occurs only in the absence of information, and the change of their codes occurs synchronously at each bit on the trailing edge of the pulse.

From the communication line, the input analog signal is fed through a filter 3, necessary for protection against high-frequency interference, to the driver 4. The duration of the received pulses is determined by a counter 9 and a decoder 10. When

5 The pulse arrivals, depending on its duration, on the first and second outputs of the decoder, 10, corresponding to 0.75T2 and 0.75TZ at T1 T2: T3 1; 2; 4, pulses appear that establish triggers 11 and 12

0 in 1 state. Reset trigger 11 and 12 occurs at times when there is a pause between pulses. The rising edge of the pulses is the sequential recording of the value of the received bits in

5 register 15. After the code in the counter of the number of received bits equals the number of bits in the received information field, the signal at the output of the decoder 6 will change its value, which will result in the formation of a short rectangular strobe pulse of the data of the shaper 7 short pulse and to reset in O through the element OR 29 of the counter 5. The pulse delayed by the block 8. is fed to the control input of the buffer register 16 and the data is written in parallel codes from the shift register 15 to the buffer register 16 The delay at block 8 is necessary Ima to complete shift operations in register 15, simultaneously gate from block 8

comes to block 17, telling him about that. that new data has been entered into buffer register 16.

Then the reception is repeated until the synchronization pulse arrives from the correspondent from the communication line. According to this pulse, the counter 5 is set to zero and the receiver and transmitter bit counters synchronize.

Claims (1)

Invention Formula A device for receiving and transmitting data containing the OR element. serially connected amplify, low-pass filter, square pulse shaper, first counter, first decryptor, first shaper of short impulse.or, first delay unit and information consumer unit, serially connected clock generator, second counter, second decoder, first the trigger, the second delay unit, the first shift register and the buffer register, the second input and output of which are connected respectively to the output of the first delay unit and the second input of the consumer unit, the second output From the second decoder, the second trigger is connected to the input of the third delay unit, the first, second outputs of the information source are connected to the first, second inputs of the second shift register, respectively; the first, second outputs of the frequency divider are connected to the first, second inputs of the multiplexer, the third and fourth inputs which is connected to the third output of the frequency divider, the second output of the information source is connected to the first input of the third counter, the output of which is connected through the serially connected third decoder, D-flip-flop and the fourth delay block connected to the fifth input of the multiplexer, the sixth input is connected to the output of the second shift register the multiplexer output is the output of the device and is connected to the first input of the element I and through the second shaper of short pulses to the first input of the frequency divider and the first input of the RS flip-flop . the output of the fourth delay unit through the element And is connected to the third input of the second shift register and the second input of the third counter, the output of the third decoder is connected to the input of the information source, the output of the clock generator is connected to the second input of the frequency divider, the output of the rectangular pulse former is connected to the second inputs of the second counter The first, second triggers and the first shift register, the output of the RS flip-flop is connected to the second input of the D flip-flop, characterized in that. In order to increase throughput, the output of the OR element is connected to the installation input of the first counter, the output of the first decoder is connected to the first input of the OR element, the second input of which is connected to the output of the third delay unit, the first output of the frequency splitter is connected to the second input of the RS flip-flop.