SU1510105A1 - Data transceiver - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to increase the capacity of the device in half-duplex operation. The device contains a clock oscillator 1, an amplifier 2, a low-pass filter 3, a shaper of 4 rectangular pulses, counters 5 and 28 numbers of received and transmitted bits, decoders 6 and 29 numbers of received and transmitted bits, shapers 7 and 27 short pulses, blocks 8,13,14 and 26 delay, counter 9 clock pulses, decoder 10 duration of input pulses, trigger 11 bit values, trigger 12 synchronization, shift registers 15 and 21, buffer register 16, information consumer block 17, dividers 18 and 22 frequencies, communication control unit 19, switches 20 and 24, multiplex The lexor 23, the AND element 25, the D-trigger 30 of the generation of the synchronization pulse, the information source 31 and the communication line 32. The goal is achieved by increasing the information transfer rate from the source 31 using the input of the divider 18, the communication control unit 19 and the switches 20 and 24, providing either termination of data transmission, or its continuation. 2 Il.

Description

31510

The invention relates to communication technology and can be used in the construction of half-duplex digital information transceivers.

The purpose of the invention is to increase throughput in half duplex operation.

Fig. 1 shows the structural electrical circuit of the device in Fig. 2 — timing diagrams, by reference to its operation.

The device contains a clock oscillator 1, amplifier 2, low-pass filter 3, shaper 4 direct pulses, 5 counts number of received bits, decoder 6 numbers of received bits, first shaper 7 short pulses, first block 8 delays, counter 9 clock pulse, decoder 10 duration of input pulses, trigger 11 bit values, trigger 12 synchronization, second 13 and third 14 delay blocks, first shift register 15, buffer register 16 information consumer block 17, second frequency divider 18, communication control block 19 the first com the stator 20, the second shift register 21, the first frequency divider 22, the multiplexer 23, the second switch 24, AND 25, the fourth block 26 of the delay, the second shaper 27 short pulses, the counter 28 the number of transmitted bits, the decoder 29 the number of transmitted bits, D-flip-flop 30 synchronization pulse shaping, information source 31, communication line 32.

The device works as follows.

Frequency divider 22 divides the input frequency of the clock generator 1 and generates three pulse sequences of different duration arriving at the inputs of the multiplexer 23. The selection of the pulse sequence and their duration at the output of the multiplexer 23 depends on the value of the signals at its control inputs. Using a short pulse shaper 27, the trailing edge of each pulse resets the frequency divider 22 counters to produce pulses with a duty cycle of 1/2. The data from the information source 31 is written in parallel code to register 21. A data tracking strobe sets a 28-bit counter in the o. The next trailing edge of the pulse with. the output of the multiplexer 23, the D-flip-flop 30 is set to the state allowing through the AND 25 element to shift the register 21 and count the number of transmitted bits by the counter 28. In addition, the control input of the multiplexer 23 sets the signal value ensuring the formation of pulses of duration T and T depending on the value of the signal at the output of the register 21. After transmitting all the data bits in the counter 28, a code is set equal to the number of transmitted bits, and the output of the decoder 29 receives a ready-to-transmit signal ol data source 31 to the incoming information. With this signal, D-flip-flop 30 is set to a state that enables the multiplexer to generate 23 synchronization pulses of duration T.

From the output of the multiplexer 23, through the switch 24, the pulses go to the communication line 32 and to the input of the amplifier 2. The amplified analog signal passes through a low-pass filter 3, necessary for protection against high-frequency interference, to the driver of 4 square-wave pulses. The duration of the received pulses is determined by the counter 9 and the deflector 10. When the synchronization pulse arrives at the first and second outputs of the decoder 10, corresponding to 0, 0.75 Tz, at j: Tj 1: 2: 4, - Lebanon triggers 11 and 12 to state 1. Reset triggers 11 and 12 occur at the moments of time when there is a pause between pulses. On the falling edge of the synchronization pulse from the output of the delay unit 14, the trigger of the frequency divider 18 switches to the inverse state and the circuit is disconnected by the switches 20 and 24, i.e. termination of data transfer. At the same time, a resolution is issued to the counter 5 received bits and the counter of the communication control unit 19.

When a signal is received from the correspondent from the communication line 32, the duration of the incoming pulses is determined by a counter 9, a decoder 10, triggers 11 and 12, and sequentially writing the value of the received bits to register 15 on the falling edge of the pulses. After the code in the counter 5 the number of bits received

will be equal to the bit in the received information field, the signal at the output of the decoder 6 will change its value, which will lead to the formation of a short square pulse strobe tracking data first shaper 7 short pulses. The pulse delayed by the delay block 8 is fed to the control input of the buffer register 16 and records the parallel code from register 15 to the buffer register 16. The delay in block 8 is necessary to complete the shift operations in register 15, while the gate from the output of block 8 enters block 17 of the information consumer, informing that new data has been entered into the buffer register 16.

Further, reception is conducted before the arrival of the synchronization pulse from the correspondent from the communication line 32. This pulse causes the next change in the trigger condition of the frequency divider 18, which leads to the prohibition of counting the number of received bits by the counter 5, setting the counter 5 and block 19 in O, and closing the circuits in the switches 20 and 24, that is. to continue data transfer.

In the absence of signals from the correspondent during the initial entry into the communication or when the communication line fails, the signal from the output of the control unit 19 with a delay relative to the beginning of the reception time longer than the required transmission time of the information field, forces the trigger of the frequency divider 18 to providing continued transmission. When this occurs, the installation of the counter in block 19 takes place in O and the forced installation stops. The delay time of block 19 should not be less than the reception time of the largest time field of data.

The use of a meter in the communication control unit 19 instead of a time delay relay with a fixed delay allows changing the delay delay of the forced installation by the unit 19 simultaneously with the frequency tuning of the clock generator.

FIG. 2 shows the waveform of the communication line when transmitting information byte by byte. The hatch-marked pulses relate to the first device for transmitting data, and the unmarked pulses to the second. On

Fig. 2a shows the waveform in the absence of information from both sources, - in Fig. 26 - with information byte by byte, in Fig. 2b - when information is transmitted only from the second source and not in the first source. In the first case, the device transmits only pulses.

synchronizing with a duration T, in the second each group of information pulses with a duration T and T is terminated by a synchronization pulse T, after which the communication link is provided to another source of information for transmitting its information field. If the field is small (no more than one byte), then switching from reception to transmission and vice versa will occur

very often, providing sources close to duplex mode. In the third case, the first device transmits only synchronization pulses, signaling the second device,

that the line is free. In this case, the transmission rate of information from the first source will increase and may become equal to 0.8 of the average transmission rate in the known device.

 invention formula

five

A device for transmitting and receiving data, comprising a series-connected amplifier, a low-pass filter, a square pulse shaper, a count of the number of received bits, a decoder of the number of received bits,

d the first driver of short pulses and the first block of delay, serially connected clock generator, clock counter and the decoder duration of the input

e pulses, sequentially connected trigger value bits and second delay unit, serially connected trigger trigger and third delay unit, sequentially

g connected to the first shift register, buffer register and information consumer block, serially connected information source and second shift register, sequentially but connected element AND, counting number of transmitted bits, decoder of the number of transmitted bits, D-trigger of formation, synchronization pulse and the fourth delay unit connected in series the second short pulse shaper, the first frequency divider and the multiplexer, the output of which is connected to the input of the second short pulse shaper, the input is amplified When connected to a communication line, the output of the rectangular pulse former is connected to the installation input of a clock counter,. with the clock input of the first shift register and with the first trigger inputs of the bit value and the synchronization trigger, the first and second outputs of the input pulse duration decoder are connected respectively to the second trigger input of the bit value and to the second synchronization trigger input, the output of the second delay unit is connected to the information input of the first the shift register, the output of the first delay unit is connected to the second inputs of the buffer replication and the consumer information block and the output of the tracking strobe data is connected to the installation The inputs of the second shift register and the counter of the number of transmitted bits, the output of the And element are connected to the clock input of the second shift register, the output of which is connected to the first control input of the multiplexer, the output of the fourth delay block is connected to the first input of the Inc element to the second control input of the multiplexer .

the output of which is connected to the second input of the element I and to the clock input of the D-flip-flop of the synchronization pulse, whose information input is grounded, and the output of the decoder of the number of transmitted bits connected to the input of the information source, characterized in that in order to increase throughput in half-duplex mode of operation , introduced the first and second switches, the control unit of communication and the second, the frequency divider, and the output of the clock generator is connected to the counting input of the first frequency divider through the first switch, output the multiplexer is connected to the communication line through the second switch, the output of the second frequency divider is connected to the control inputs of the first and second switches and to the installation inputs of the counter of the number of received bits and the communication control unit, the output of which is connected to the installation input of the second frequency divider, output three the delay unit is connected to the clock input of the second frequency divider, and the output of the clock generator is connected to the control input of the communication control unit, made in the form of a counter, the counting input of which is a reg -insulating and installation input - the control

Claims (1)

'Claim A device for transmitting and receiving data containing a serially connected amplifier, a low-pass filter, a rectangular pulse shaper, a counter of the number of received bits, a decoder of the number of received bits, a first short pulse shaper and a first delay unit, a serially connected clock, a clock counter and a decoder the duration of the input pulses, a serially connected trigger of a bit value and a second delay block, a serially connected trigger of synchronization and a third block aderzhki serially connected first shift register, the buffer register and an information consumer, source of information serially connected and a second shift register connected in series element and the counter number of transmitted bits, the decoder of the transmitted bit, D-flip-flop formation. a synchronization pulse and a fourth delay unit, sequentially connected to a second short pulse shaper, a first frequency divider and a multiplexer, the output of which is connected to the input of the second short pulse shaper, the amplifier input is connected to a communication line, the output of a rectangular pulse shaper is connected to the installation input of a clock pulse counter, . with a clock input of the first shift register and with the first trigger inputs of the bit value and synchronization trigger, the first and second outputs of the input pulse width decoder | 5 are connected respectively to the second input of the bit value trigger and to the second input of the synchronization trigger, the output of the second delay block is connected to the information input the first shift register, the output of the first delay block is connected to the second inputs of the buffer register and the consumer information block, the output of the data tracking strobe is connected to the setting '5 inputs of the second shift register and the counter of the number of transmitted bits, the output of the And element is connected to the clock input of the second shift register, the output of which is connected to the first control input of the multiplexer, the output of the fourth delay unit is connected to the first input of the And element and to the second to the control input of the multiplexer, the output of which is connected to the second input of the And element and to the clock input of the D-trigger for generating a synchronization pulse, the information input of which is grounded, and the output of the decoder of the number of transmitted bits is connected to a source of information, characterized in that, in order to increase throughput in half-duplex operation, the first and second switches, a communication control unit and a second frequency divider are introduced, and the output of the clock generator is connected to the counting input of the first frequency divider through the first switch, the output the multiplexer is connected to the communication line through the second switch, the output of the second frequency divider is connected to the control inputs, ladies of the first and second switches I. 'U and to the installation inputs of the counter of the number of received bits and the communication control unit, the output of which is connected to the installation input of the second frequency divider, the output of the third delay unit is connected to the clock input of the second frequency divider, and the output of the clock generator is connected to the regulatory input of the communication control unit in the form of a counter, the counting input of which is regulating, and the installation input is managing. Tz tz RGNGYAGL ---- Tz t ₃ dp a Η π π π π π p p l οππππππππ’Γίήπππππππππ