RU1771076C - Bipulse signal receiving device - Google Patents

Abstract

The device contains: 1 differentiating unit (1), 1 delay unit (2), 1 OR element (3), 1 AND element (4), 2 triggers (5, 6), 1 shift register (7), 1 pulse counter ( 8). 1-4-6-7. 1-2-3-5-4. 1-3, 5-8-9, 5-7, 8-8. 2 ill.

Description

Ј

ate

.1

sl s |

about

4

ON

The purpose of the invention is to increase the reliability of data reception.

This goal is achieved by the fact that the second trigger trigger the pulse counter, and the output of the differentiating unit is connected to the first input of the element And, the first, is introduced into the device for receiving bi-pulse signals containing a differentiating block, a delay unit, an AND element, an IL element, a trigger and a shift register. the input of the OR element and through the delay unit with the second input of the OR element, the output of which is connected to the counting input of the first trigger, the inverse output of which is connected to the second input of the AND element, and the direct output to the synchronizing input the shift register input and the counting input of the pulse counter, the zero input of which and the control input of the shift register are connected to the output of the pulse counter, the output of the element And is connected to the counting input of the second trigger, the output of which is connected to the information input of the shift register, the outputs of which are information outputs of the device, the control output of which is the output of the pulse counter.

A comparative analysis with the prototype shows that the claimed device is distinguished by the presence of new elements: a trigger and a pulse counter, and new connections in the existing elements.

In FIG. 1 shows a structural diagram of a device; in FIG. 2 - voltage diagrams explaining the operation of the device.

In FIG. 1, the following notation is introduced: 1 - differentiating block, 2 - delay block, 3 - OR element, 4 - AND element, 5, 6 - first and second trigger, 7 - shift register, 8 - pulse counter.

The elements of the device are connected as follows: the input of the differentiating unit 1 is the output of which is connected to the input of the delay unit 2, the first input of the OR element 3 and the first input of the AND 4 element, the output of the delay unit 2 is connected to the second input of the OR element 3, the output of which is connected to the counting input of the first trigger 5, the inverse output of which is connected to the second input of the And 4 element, and the direct one to the synchronizing input of the shift register 7 and the counting input of the pulse counter 8. The output of the pulse counter 8 is connected n to its input of the installation in the zero state, as well as to the control input of the shift register 7. The input of the element And 4 is connected to the counting input of the second trigger 6, the direct output of which is connected to the information input of the shift register 7, the outputs of which

are the information outputs of the device, the control output of which is the output of the pulse counter 8.

The device operates as follows.

After the functioning of the device, we will perform using voltage diagrams.

The input device (Fig, 2A)

0 is a sequence of bi-pulse recovery signals, wherein it is believed that a single symbol is also received before this.

In order to form a sequence of synchronizing pulses (SI) by the differentiating unit 1, the fronts of the received packets are differentiated (Fig. 2 b). Using the delay unit 2, the delay of differentiating pulses is delayed by half the clock period (Fig. 2c), which are fed to the second input of the OR element 3. At the output of the OR element 3, a sequence of differentiating pulses is formed

5 (Fig. 2d), which enters the counting input of the first trigger 5. At the direct and inverse outputs of this trigger, SI sequences shifted by 1/2 T are generated (Fig. 2e, e). Using the And 4 element (on the second

0 input of which the SI sequence is shifted (Fig. 2e), only differentiation pulses selected in the middle of the bi-pulse interval are selected (Fig. 2g).

5 These pulses correspond to a change in binary values in the received bi-pulse signals. The SI sequence from the direct output of trigger 5 (Fig. 2e) is used as the SI.

0 writing data to shift register 7 (using this register, the serial data format is converted into a parallel, convenient for information consumption. Pulse counter

5-8 counts the number of received symbols. After each n-th received symbol (n is the number of characters in the message), a single signal is generated at its output, by which the next received message is sent by the parallel code from the shift register 7 to the information consumer.

For proper operation of the device at the initial moment of operation of the device, the first and second triggers 5, 6 are set to zero. For the organization of data transmission, a single double pulse is transmitted at the beginning, in which it is assumed that it was preceded by a null binary symbol. This symbol is necessary for the proper organization of data transmission. It is followed by a stream of data. Messages consisting of n bits follow each other without intervals.

Claims (1)

SUMMARY OF THE INVENTION A device for receiving bi-pulse signals, comprising a differentiating unit, a delay unit, an AND element, an OR element, a first trigger and a shift register, characterized in that, in order to increase the reliability of receiving data, a second trigger and a pulse counter are introduced into it, and the output differentiating unit is connected to the first input of the AND element, the first input of the OR element, and 0 5 through the delay unit - with the second input of the OR element, the output of which is connected to the counting input of the first trigger, the inverse output of which is connected to the second input of the And element, and the direct output - with the synchronizing input of the shift register and the counting input of the pulse counter, the input to the zero state whose operation and the control input of the shift register are connected to the output of the pulse counter, the output of the element And is connected to the counting input of the second trigger, the output of which is connected to the corresponding input of the shift register, the outputs of which are Information outputs of the device, the control output of which is the output of the pulse counter.