SU705494A1 - Sequence code receiver - Google Patents

Description

The second K-flip-flop is connected to the setup bus to zero, the first input of the fourth NAND element is connected to the clock pulse bus, the inverse output of the second D K-flip-flop is connected to the second input of the fourth NAND element. Fig, 1 presents a block diagram of the proposed device. The device contains the following elements: element 1 AND-NOT, element 2I-4I-2ILI-2NE,. elements 3 NOT, 3K-trig ger 4, elements 5, 6 AND-NOT; information input device 7, bus 8 set to zero, bus 9 clock pulses, output 10 of the NAND element, output 11 of the element 2I-4I-2ILI NOT, direct output of the PC trigger 12, inverse output 13 3 K-trigger, output 14 elements AND - output .15 elements NAND, direct output 16 of the 3K register trigger, direct output 17 DK of the register trigger, element 18 AND-NOT, element 19 NOT, D K-flip-flop 20, output 21 of the element NO, inverse exit 22. 3 K-trigger. FIG. Table 2-7 shows the time diagrams of the device operation. The device works as follows. The information pulses of the code sequence arriving at the input of the proposed device, as a rule, do not coincide in time with the synchronizing (shear) pulses accompanying them, since they come from different sources via communication lines having different lengths. belonging to the same code sequence, have the same time shifts with respect to the corresponding synchronization pulses over the entire length of the received code, so there is a need to set the times The process of receiving a single code of the combination will perform the necessary switching of its IB depending on the error of the above pulses. To carry out this commutation and, therefore, reliable recording of information into the shift register in the first discharge of the received code, there must always be one unit (marker). Before starting to receive the code, a negative polarity pulse is sent to the zero bus, and as a result, at outputs 12, 14 , 16, 17 there is a logical O (low potential), and at outputs 10, 11, 13, 15, 22 logical 1 (high potential). The above switching of the received code is performed by extracting the first shear pulse from the series and polling it with the help of its information 3 K-flip-flop 4. The shift of the pulse is sent to Is 9 at the moment it arrives at information input 7 to 944 of the next code. The first shift pulse passes through element 18 NAND, since its second input contains a high level of potting. From the output of element 18 NAND, this shift pulse through element 19 does NOT flow to the C inputs of JK triggers 4 and 20. At the end of this pulse, the OK trigger 20 switches and a low potential level appears at its inverse output 22 to the second input of the element 18 NAND, so that the subsequent shift pulses do not pass through the element 18 NAND. At the same time, the selected shift pulse interrogates the state of the LC trigger 4. At the same time, if the information pulse of the received code appears at the device's input after the end of the shift pulse (see Fig. 7), then the D K-trigger switches to state 1 In all the other cases considered below for receiving information, the LC trigger 4 does not change its initial state. Consider several cases of receiving information. Timing diagrams for receiving information are shown in FIG. 2-7. At the same time, in these diagrams, for simplicity of presentation, a code consisting of one information pulse is shown. .. An information pulse arrives and ends before the arrival of a shift pulse (Fig. 2). From the input 7, the information of the code is fed to the input of the element AND of the element 2 2И-4И2Ш1И-НЕ, at the input 11, a logical O appears, and at the output 14-logical 1. With the end of the information pulse, this state of the elements remains. It changes only with the appearance of the blast pulse. Moreover, with its beginning at output 15, logical O appears, and with its ending at outputs 11-21, logical 1. 3 K-trigger of the first bit of the shift register switches to state 1, the trigger on elements 5 and 6 returns to the initial state p e, and O appears at outputs 21 and 22. If the second code of the received code contains O (low potential, then with its nQmjiet eM the device element states are preserved, and at the end of the next shift pulse the first discharge trigger the shift register switches to state O, the trigger of the second bit in 1. If the second bit of the received code is 1 (high potential), then with its appearance the state of the device elements will change similarly to 5;.,., .. changes caused by the appearance; jiepBoro information pulse. In this case, at the end of the shift pulse, coof Sffiif №i№ fB, the discharge is accepted (Г1 ШТ й 5 гийе7 the first discharge of the register does not match the second digit of the register РТ11оЧаетсяс Т;; register without distortion. The information pulse arrives before the beginning of the shift pulse, and ends before the end of the latter (Fig. 3). The information impulse sent to the input of the device causes ffleJ a,. output 11 is logical O, and at output 14, logical I. At the arrival of a shear pulse, the states of outputs 11 and 14 do not change, and at output 15 a logical O appears, and at output 21, a logical potential output 11 changes from O to G With the end of the shift pulse D the K-trigger of the first discharge of the shift register is transferred to state 1, the trigger on elements 5 and 6 returns to the initial state, and at outputs 21 and 22 O appears If in the second category of the received 1: ODS kakhbyps O, then with its appearance The device's elements are saved, and the window of the next shift of the three bits of the first bit of the register is switched to the state O, the trigger of the second bit is 1 if the second bit of the received code contains 1, then with its riDflBneHH M 6cfo fl the device changes in the same way as the Bbi3BaHHbiM ftepief% H $ opMa impulse. In doing so, tib6K6fl4 & The scientific research institute of the shift pulse of the corresponding code bit, the state of the first bit of the register does not change, and the second bit of the register is switched to status. The shift pulse pulses are in the information field - r- - - - if rt4- . onnsh impulse on the front and rear edges (Fig. 4). 1st;;;; SHOCKING An informational impulse causes the occurrence at the beginning of 11 of a logical O, which is fed to the input of the element 5 L-2iiSi -ir h V --- -the appearance at output 14 of logical G output 15 - logical O. At the end of the shift pulse and the K-flip-flop Shn register switches to I, and the flip-flop on elements 5 and 6 returns to the - initial state the If O is contained in the second digit of the received code, then with its appearance m5aash "" e 5 VZh1 "(H | av CONDITIONS of the device elements are saved, -Sfilf f S: -, .-- 11g Et; -T: G - Lg-- -.a after the end of the second session, the -r -liiViV / i -fi ii iiiui "it iii fiiii iiMilf HMr J If the second digit of the code is 1, then after the end of the second shift pulse: the current and the fifth section of the regulator is not changed, and the second digit of the register is switched to the state 1.. with a shift pulse (Fig. 5). With the arrival of the shforming and shearing pulses at output 11, a logical O appears, which is fed to the input of element 5 AND-NOT, and therefore, at output 14, logical 1 appears and in code 15, logical A. On the falling edge of the first shift pulse, the trigger of the first register bit switches to state 1, and the triggers on elements 2, 3, and 5, 6 return to the initial state. If O contains in the second bit of the code being pressed, then at the end of the second shift pulse, the trigger of the first register bit switches to the O state, and the second bit trigger is set to 1. If in the second bit the received code contains 1, then at the end of the second the shift pulse of the state of the first register bit does not change, and the second bit of the register switches to state 1. The information pulse arrives after the beginning, and the shift pulse, and ends with the start after its end (Fig. 6). At output 11, a logical O appears with the arrival of an information pulse, which enters the input of element 5 AND-NOT, causing the appearance at output 14 of logical 1, and at output 15, logical O. With the end of the information pulse, the status of outputs 11 and 14 preserved. With the end of the first shift pulse at output 15, logical 1 appears, and the first-bit SJ trigger of the register switches to state 1. Before the start of the next shift pulse, the triggers on elements 2, 3, 5, and 6 return to their initial state. If on the second level the code contains 5KITS O, then with its occurrence, the state of the device elements is preserved, and at the end of the second shift pulse the first register bit trigger switches to the O state, the second register bit trigger is 1, if in the second bit the code contains 1, then its appearance of the state of the elements. ,, l-mi-jr-. ... ,, ui .., the devices are changed in the same way as the changes; . - .- ... .. ... .. m, caused by the per1в0 (L informational they yUzhs15m. At the same time, at the end of the impulse

the shift corresponding to the second bit of the code, the state of the first bit of the register does not change, and the second bit switches to state 1.

The information pulse comes after the end of the shift pulses (Fig. 7). On the falling edge of the shear pulse emitted by elements 18–20 and appearing at exit 21, there is an emergency. Trigger 4 switches to state 1. Logical 1 from output 12 is fed to the first input of element 1 AND-NOT. With the arrival of an information pulse, the output of the element 1 appears a logical O, which, arriving at the S input of the PC trigger of the first register bit, switches it to state 1. With the end of the information pulse at output 10, the potential changes from 0 to 1, and the recorded unit is stored in the first digit of the register until the next cwBHl-aioihero pulse arrives, which shifts it in the second digit.

If in the second category the code contains

devices are saved, i.e. Code 01 will be stored in the register.

If in the second bit the received code contains 1, then it goes through element 1 to the S input of the K flip-flop of the first register bit and switches the latter to state 1. In this case, after the device enters the device, two unit code characters code 11 is entered into the shift register.

Thus, from the considered BMjpiOV slips, that the accuracy of the entry in the shift register of a sequential code entering the input of the proposed device does not depend on the temporal arrangement of its axis relative to the shift pulses, which makes it possible to increase the reliability of information reception ..

Claims (2)

1. USSR Author's Certificate No. 378930, 1СЛ. G 08 C 19/28. 2. USSR author's certificate number 526940, .kl.S 08 C 19/28, 09/13/74 (prototype). . "-. -VijNfeVy -rr here fe Schg DjpfeSH j; eв 4 - / 1st, yy ..u.; ...., ", u iagl / .. Q. A- :.) -; --- VsM f YIJAYAYY4 K 1yZhVZZ in Y SCHI Й Chy5ch g Y a B 3 t- iwvb SiiSBi:, - -i .jOffiK- «chi. p r lal r icS - a: - ET gr-; : 4;: S Ai:, .i aJ t H8 g j g e tfeaESgfe € g: - ife-a: & sga. ..tag ..: C-g-UCH: ,, idiaaJ tevgM ff5i T. .T .. .J.j ": aMgt tiAtfaj tmaai a aaaHs. 15  ////// / //// //// 7 / one-; № 5 / / / ff / 7 I I