SU1614105A1 - Pulse timing device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation, computing and communication devices for controlling counting circuits, encoders. The purpose of the invention is the extension of the field of application by providing work with input signals of various types - the introduction of three elements coinciding 8, 9, 10. The device also contains triggers 1, 2, 3, 4, elements of coincidence 5, 6, 7, input buses 13, 15, 16, 17, bus 14 "Stop", output tires 11 and 12. 2 Il.

Description

AND

1

The invention relates to a pulse technique and can be used in automation devices, computing and communication devices for controlling counting circuits, encoders, etc.

The purpose of the invention is to expand the scope by providing work with input signals of various kinds.

FIG. 1 shows the electrical functional scheme of the device; in fig. 2 - time diagrams that show his work.

Pulse synchronizer contains triggers 1-4, elements 5-10 matches, R-inputs of the first 1 and second 2 triggers are connected with outputs of the first 5 and second 6 elements of the match, respectively, the output of the third element 7 of the match is connected to the first output bus 1 T, forward the fourth coincidence element 8 is connected to the second output bus 12 and the first S input of the second trigger 2, the direct output of which is connected to the C input of the third trigger 3, the inverted and direct outputs of which are connected to the first inputs of the third 7 and fourth 8, respectively eleme Coincident coincidence, the second inputs of which are connected to the output of the fifth coincidence element 9, the first and second inputs of which are connected respectively to the first input bus and stop bus 14, the second S input of the second trigger 2 is connected to the R-BXO of the first trigger. 1, the S-input of which is connected to the second input bus 15 and the first input of the first coincidence element 5, the second input of which is connected to the third input bus 16 and the first input of the sixth matching element 10, the second input of which is connected to the forward output of the first trigger 1 and The R input of the fourth trigger 4, the S input of which is connected to the output of the sixth TO match element, direct output to the third input of the first matching element 5 and the first input of the second matching element 6, the second input of which is connected to the fourth input bus 17.

The synchronizer 17 operates as follows.

The input bus 13 receives information in the form of a synchronous or asynchronous sequence of pulses (Fig. 2a). The input bus 14, the bus Stop, serves to supply a inhibitory potential. When the power is turned on, all the synchronizer triggers (Fig. 2, moment to) can be in any position, for example, in the following initial state: triggers 1, 3 and 4 - in the state O, trigger 2 - in the state 1.

In the initial state (Fig.2l) the resolving potential from the inverse output

trigger 3 allows information through element 7 to form on the output bus 11 a synchronous flow of pulses (Fig. 2o). The inhibitory potential from the direct output 5 of the trigger 4 does not allow information pulses through the element 8 to pass to the output bus 12 and generate an asynchronous stream of pulses (fig.2n). Using bus 14, element 9 is controlled and

0 form with the help of permitting or inhibiting potentials pulse flows on tires 11 and 12.

In order to get a distortion of the orderly impulse sequence (in

5 given the input sequence), an asynchronous control signal is fed to the bus 15 (FIG. 2d). It sets the trigger 1 to state 1, the resolving potential (figd) from its output enters

0 to the first entry of element 10, preparing

passing through this element of momentum

launch. Start pulse (figv) enters

with bus 16, ahead of the input information.

If an asynchronous control signal designed to introduce distortions in the information from bus 13 does not arrive before the start pulse arrives, the synchronizer works without introducing distortions (stress plots for the period ti-t2

0 in the timing diagram of FIG. 2).

The asynchronous signal is synchronized with the closest starting pulse, received after the arrival of the asynchronous signal. Pulse Synchromator

5 (type 1) the closest (first) pulse of information received after the coincidence of the control signals coming from tires 15 and 16 (period t2-t3 in the timing diagram of FIG. 20). This happens as follows. The signal of the type 16 passes to the output of the cooling element 10 (FIG. 2e) prepared for this in advance, due to the receipt of the signal from the bus 15. Then it goes to the S input of the trigger 4 and sets it to state 1 (FIG. .2g) In this case, the permissive potential arrives at the inputs of elements 5 and 6. The impulse does not pass through element 5, since a barring potential enters from this bus 15 on this element. The launch takes place through the element 6 signals arriving at its other input bus 17 (fig.2b). The information in this case passes from the output of the element 6 (Fig. 2i) to the R input of the reset trigger 2, setting it (its first front) to the state RhN. Then the signal from the output of trigger 2 (differential 1 0) is fed to the counting input of trigger 3. its transfer from the state O to state 1. Element 7 receives

prohibiting, and the element 8 - resolving potentials. Since the information on the bus 17 is delayed with respect to the information on the bus 13, the first information pulse passes to the bus 11, and the pulse synchronizer works in the same way as in the period ti-t2. But as soon as trigger 2 changes its initial state, the second information pulse cannot pass through element 7 to bus 11 (Fig. 2o), but passes through element 8 to bus 12 (unlike period ti-t2, fig. 2m ). From the output of element 8, the pulse arrives at the first S-input of trigger 2 and sets it to 1. Another (second) pulse of delayed information sets trigger 2 to O with its front (Fig. 2k). The signal from the output of trigger 2 (difference 1 - 0) goes to the C input of trigger 3, changes its state to the opposite, now from 1 to O (fig.2l, m). Now elements 7 and 8 receive the enabling and inhibiting potentials, respectively, the bus 11 receives undistorted information, and there are no error pulses on bus 12, i.e. Further, the synchronizer works as in the period ti-t2.

The pulse synchronizer provides distortion of one pulse when a control signal arrives on the bus 15 (FIG. 2d). For this purpose, a synchronizer circuit is designed in such a way that, subject to the presence of O on bus 15, no further distortion of the pulses occurs, looking at the further arrival of the trigger pulses. This mode of operation of the synchronizer is shown in FIG. 2, period t3- t4. The next start pulse, received before the removal of the potential O from the bus 15, only confirms the state of the trigger 1, the passage to its installation input through the element 10. Through the element 5, the shock pulse cannot pass. No changes in the synchronizer operation, work; performed without distortion, as in the period ti-t2.

In the absence of a control signal on bus 14, the next start pulse received on bus 16 confirms state 1 of trigger 4 and, having passed through element 5 (FIG. 2h), enters the inputs of trigger 1 and 2, setting them to state O and 1, respectively (FIG. 2g, u). Potential O from the output of trigger J is fed to the R input of trigger 4 and (after the start pulse has elapsed), sets this trigger to state 0 (FIG. 2G),

From the time t4, the operation of the pulse synchronizer is repeated: the periods alternate in different order depending on the combination of signals on the input buses.

The proposed device is used in circuits that do not have paraphase input signals, in circuits that work not only with continuous sequences of pulses, but also with bursts of pulses (due to synchronization of an asynchronous control signal) to control encoders (due to the ability to distort a certain number of pulses on certain places information sequence). This device allows you to more deeply check the operation of counting and shearing schemes (not only by the final result, but also to check the operation of individual bits of the counting schemes), and also to check the operation of encoders using a synchronizer, reducing the time of just discrete testing (computers, channels connection), the cost of its rental and operation.

Claims (1)

Invention Formula Pulse synchronizer containing first to fourth triggers, R-inputs of the first and second triggers are connected to the outputs of the first and second match elements, respectively, the third match element, the output of which is connected to the first output bus, from the first to the fourth input buses, Stop bus and second output bus, which is related to the fact that, in order to expand the scope of application by providing work with input signals of various kinds, the fourth, fifth and sixth elements of the match are introduced into it, the output of the first The x is connected to the second output bus and to the first S input of the second trigger, the direct output of which is connected to the C input of the third trigger, the inverse and direct outputs of which are connected to the first inputs of the third and fourth match elements, respectively, the second inputs of which are connected to the output the fifth coincidence element, the first and second inputs of which are connected respectively to the first input bus and to the stop bus, the second S input of the second trigger is connected to the R input of the first trigger, the S input of which is connected to the second input bus the first input of the first match element, the second input of which is connected to the third input bus and the first input of the sixth match element, the second input of which is connected to the direct output of the first trigger and to the R input of the fourth trigger, the S input of which is connected to the output of the sixth coincidence element , direct output - with the third input of the first match element and the first the input of the second match element, the second input of which is connected to the fourth input bus. a b in g d e Well 3 and to l m n 2