SU1287184A1 - Switching device for multichannel check and control systems - Google Patents

Abstract

The invention relates to the field of automation and instrumentation technology. Can be used; but in control and monitoring systems. The purpose of the invention is to increase the reliability of the device. It is achieved in ensuring the switching of keys in a strict sequence when the signals appear as a result of the failure of the decoder, as well as when the decoder fails (disappears impulses), i.e. with stable failures and failure in the decoder, subject to

Description

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nor a strict sequence of information pulses at the device input. To achieve this goal, a control unit 11 was introduced into the device, and a delay element 12 was inserted into each of the (M-2) parallel circuits 5, and new functional connections were formed. In addition, the device contains a counter 1, a decoder 2 with M outputs, (M-1) keys 3, an element OR 4 with (M-1) inputs, (M-1) parallel circuits 5. Each of the 5 circuits has an RS-flip-flop 6, the element OR 7, the element AND 8. And each of the parallel circuits 5 with the second one through (M-1) contains the second element AND 9, the second through (M-2) is the second element OR 10, the device allows you to eliminate failures the decoder and the counter, ensures proper functioning at the occurrence of private pulses, at one or more outputs of the decoder, which increases the reliability of the device, and If the key is not switched, it displays the Failure indication. 1 PC.

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The invention relates to automation and instrumentation technology and can be used in control and monitoring systems.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by ensuring the switching of keys in a strict sequence when lssh signals appear as a result of the failure of the decoder, as well as if the decoder fails (missing pulses), i.e. in case of stable failures and failures in the decoder, subject to receipt of a strict sequence of information pulses at the device input.

The drawing shows a functional diagram of the device.

The switching device for multichannel monitoring and control systems contains counter 1, the counting and installation inputs of which are respectively connected to the information and control inputs of the device, the outputs of the counter are connected to the n inputs of the decoder 2 to the N-2 outputs (where n 1,2,3 .. . p) (M-1) of keys 3, the element OR 4 with (Ml) inputs, (M-1) of parallel circuits 5, each of which contains an RS flip-flop 6, the first element OR 7, the first element AND 8. Forward the output of the RS flip-flop 6 and the output of the first element OR 7 are connected respectively to the first and second inputs of the first About element 8, the output of which is connected to the input of the corresponding key 3, the outputs of the decoder 2 from the second to AND connected to the first inputs of the first elements OR 7 (M-1) of parallel circuits 5, respectively, the second inputs of the first elements OR 7 (M-1) parallel circuits combined. S-input RS flip-flop first

parallel circuit is connected to the installation input of the counter 1. Each of the parallel circuits 5 from the second through (M-1) contains the second element And 9, and the second through (M-2) - the second element

OR 10, the output of which is connected to the R-input of RS-flip-flop 6. The first inputs of the second elements OR 10 parallel circuits 5 second to (M-2) are connected to the 8-input RS-flip-flop 6 of the first parallel circuit 5. A block is entered into the device 11 controls, and each of (M-2) parallel circuits 5 contains a delay element 12, the input of which is connected to the output of the first element AND 8 of the previous parallel circuit 5, and the output to the first input of the second element And 9 following a parallel circuit 5. The output of the second element And 9 of the second parallel circuit is connected to the S-input of the RS-flip-flop 6 of this pair circuit 5 and with the R-input of the RS-flip-flop 6 of the first parallel circuit 5. In parallel circuits from the second to (M-1), the output of the second element And 9 is connected to the S-input of the RS-flip-flop 6 of this parallel circuit 5 and with the second the input of the second element OR 10

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the previous parallel circuit 5. The second inputs of the second elements And 9 parallel circuits 5 with the second one (M-1 combined and connected to the control input of the device and the first input of the control unit 11. R-input RS-trigger 6 (M-1) parallel circuit 5 is connected to the first input of the second element OR 10 (M-2) of the parallel circuit 5 and the second input of the control unit 11, the third input of which is connected to the output of the element OR 4 with (M-1) inputs. The inputs (M-1) of the keys 3 connected respectively to the inputs of the element OR 4 with (M-1) inputs. The combined second inputs of the first elements OR 7 (M-1) n The parallel circuits 5 are connected to the output of the Failure of the control unit 11, which contains the element OR 13, the RS flip-flop 14, the element AND 15, the element 16 and the delay element 17, whose input is connected to the element OR 13 and is the first input of the control unit 11. The output of the delay element 17 is connected to the first input of the AND 15 element, the output of which is connected to the S input of the RS flip-flop 14, the R input of which is connected to the output of the OR element 13. The second input of the latter is the second input of the control unit 11, the third input which through the element NOT 16 is connected to the second input of the element 15. my output RS-flip-flop 14 is connected to the output control unit 11 Failure apparatus for switching multi-channel monitoring and control systems work sledztoschim manner.

In the initial state, the pulse arriving at the control input of the device is set to the zero state of the RS-flip-flops 6 of all parallel circuits, except the RS-flip-flop 6 of the first parallel circuit 5, which is set to one by this pulse. The same signal resets the counter 1 and sets the RS flip-flop 14 to the zero state. From the output of the element OR 4 s (M-1) the inputs to the input of the element NOT 16 receive a zero potential, from the output of the element NOT 16 the resolving potential enters the input of the element 15,

With the arrival of the first clock pulse at the counting input +1 of the counter 1, the switching potential appears at the first output of the decoder 2

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which through the element OR 7 and the element AND 8, prepared for operation by RS-trigger 6, set in one state by a pulse from the control input, goes to the corresponding key 3, switching it through delay element 12 to the input of element AND 9 by preparing it for opening, and also through the element OR

10 4 s (M-1) inputs are fed to the input, the element is NOT 16, the zero potential from the output of which element 15 is closed. The first clock pulse is also fed to the input element 17

 5 delay, on the R-input of the RS-flip-flop 14 and on the second inputs of the elements And 9, and the delay time of the signal in the delay elements 12 is equal to the duration of the clock pulse than

20, the simultaneous pinching at the inputs of the element AND 9 of the first clock pulse of the switching potential, coming from the output of the element 8, is eliminated, therefore the RS flip-flop 6 of the second parallel circuit remains in the zero state. The time delay of the signal in the delay element 17 is equal to the time from the moment of arrival of the clock pulse at the +1 input

30 of the counter 1 until the closure of the element AND 15 is the zero potential from the output of the element 16, therefore the RS flip-flop 14 remains in the zero state.

I Upon receipt of the second clock

pulse, it passes to the second inputs of the elements And 9, but passes only through the element And 9 of the second parallel circuit 5, prepared for the opening

40 second switching potential from the output of the element And 8 of the first parallel circuit 5, and is fed to the S-input of the RS-flip-flop 6 of the second parallel circuit 5, set it to one

The 45 state, and the R input of the RS flip-flop 6 of the first parallel circuit 5, sets it to the zero state.

The positive potential from the direct output of the RS flip-flop 6 of the second parallel circuit is prepared for operation element 8, to the second input of which through the delay between the arrival of the second clock pulse at the +1 input of counter 1 and the establishment of the switching potential at the second output of the decoder 2 receives the switching potential (through the element OR 7), which passes through the given data element AND 8 and enters

5 12

to the corresponding key 3, as well as to the input of the delay epimete 12 and through (M-1) the input element OR 4 with (M-1) inputs - to the input of the element NOT 16. In this case, the element 9 of the third parallel depy remains closed, RS - the trigger 6 of the third parallel circuit is in the zero state, the AND 15 element remains closed, and the RS-flip-1 ger 14 remains in the zero state. I Further, the operation is similar, and when the RS-trigger of the subsequent parallel circuit 5 is set to one, the RS-trigger 6 of the previous parallel circuit 5 is set to the zero state by a pulse from the output of the element And 9 of the subsequent parallel circuit 5, connected to the R-input of the RS-trigger 6 of the previous parallel circuit 5, for RS-flip-flops 6 from the second (M-2) parallel circuits through. element OR 10, and for RS-flip-flop 6 of the first parallel circuit 5 - directly.

After the switching of the last key 3, the circuit returns to its initial state with a reset pulse arriving at the control input of the device. In the event of a spurious signal at any output of the decoder at the outputs of the elements And 8 there is a zero potential. At the output of the element OR 4 there is also a zero potential, which means that at the output of the element NOT 16 there is a single potential,. the preparatory element for operation AND 15. The circuit is ready for the arrival of the next clock pulse and commutation of the next key 3.

If the decoder fails — the pulse disappears — the device does not allow switching of one of the keys and corrects the failure in strict accordance with the number of received clock pulses. In case of loss of a pulse at the second output of the decoder 2, when the second clock pulse arrives at the input of the counter 1, a failure occurs - there is no signal at the second output of the decoder 2. The clock pulse, with the receipt of which the failure occurred, enters the delay element 17 and through the OR element 13 at the R input of the RS flip-flop 14, at the second input of the And 9 element of the second parallel circuit 5, prepared for opening by a single potential,

from the output of the element 12 of the delay of the first parallel circuit 5. This pulse sets the RS-flip-flop 6 of the second parallel circuit 5 to be set to one state, and the RS-flip-flop 6 of the first parallel circuit 5 to zero. Element And 8 of the second parallel circuit 5 is prepared for operation as a result of a failure in the decoder, its potential remains zero. Element And 15 remains prepared for operation by a single potential coming from the output of the element NOT 16. At the end of the delay time of the delay element 17, the second clock pulse, having passed through the element 15, sets the RS flip-flop 14 into one state. The potential from the direct output of the trigger 14 is supplied to the second input of the element AND 8 through the element OR 7 and passing through it switches the second key 3, which is not passed. All the subtraction processes are terminated before the next clock pulse arrives at the device input, which prevents the clock pulse from passing.

When signals appear on two or more outputs of decoder 2, one of which is switching, and the rest is false, switching of key 3 produces only a true signal fed to parallel circuit 5 prepared for RS-trigger 6 of this parallel circuit 5 set in a single state clock pulse, on receipt of which the failure occurred. False signals do not pass through parallel circuits 5, since all elements AND 9 of other parallel circuits 5 are closed by a zero potential from the direct outputs of the RS flip-flops 6.

The situation when all the potentials at the outputs of the decoder 2 are false is similar to the appearance of one false signal in the device, and in this case it works similarly to the indicated mode a false signal. The device is operational and with a complete failure of the system (stable failure) of the counter 1 or the decoder 2 and sequentially switches the keys 3 in accordance with the clock pulses arriving at the information input of the device.

The proposed device allows to eliminate the failures of the decoder and the counter.

ka, ensures the correct functioning when private pulses appear at one or several outputs of the decoder, which makes the device reliable, and if there is no key switching, it provides an indication

Renouncement,

Claims (1)

Invention Formula A switching device for multichannel monitoring and control systems, containing a counter, the counting and installation inputs of which are respectively connected to the information and control inputs of the device, the counter outputs are connected to the p inputs of the decoder to the M Z outputs (where n 1,2,3 ... p ), (M-1) keys / element OR with (M-1) inputs, (M-1) parallel circuits, each of which contains an RS flip-flop, first OR element, first AND element, direct RS-flip-flop output and the output of the first element OR are connected respectively with the first and. second inputs of the first The element AND, whose code is connected to the input of the corresponding key, the outputs of the second to M decoder are connected to the first inputs of the first OR elements (M-1) of parallel circuits, respectively, the second inputs of the first OR elements (M-1) of parallel circuits are combined, S-input The RS flip-flop of the first parallel circuit is connected to the installation input of the counter, each of the parallel circuits from the second through (M-1) contains the second element AND, and the second through (M-2) the second element OR, the output of which is connected to the R input RS-flip-flop, the first inputs of the second elements of WL parallel The second to second circuits (M-2) are connected to the S-input of the RS flip-flop of the first parallel circuit, about one and two. In order to increase reliability, a control unit is inserted. In each (M-2) parallel circuits there is a delay element, the input of which is connected to the output of the first ten 15 20 25 thirty 35 40 45 50 the element And the previous circuit, and the output from the first element And the trace of the circuit, the output of the second And the second parallel to the S-input RS-flip-flop circuit and from the R-in the first parallel parallel chains c to the output of the second element j with S - by the input of the RS-flip-flop circuit and from the second element OR of the stitching circuit, the second elements And parallel along (M-1) are connected to the control input to the first input of the RS-flip-flop unit (M-1) pa connected to the first inlet OR (M-2) pair by the second input of the block whose input connects the SHSh element with (M-1) (M-1) keys is connected to the inputs; the element is the inputs combined by the first elements of shsh chains are connected to the control unit. The device according to the fact that the control validity checker contains an electronic trigger, an AND element, a delay element, an input to an element with an OR element, and an output input of the control unit of a delay element that is an input of an AND element, you are connected to the S-input. element OR, the second is the second input, the third input is NOT connected to the input element voltage, and you are directly connected to the output of the control. Compiled by V.Sleptsov Editor S.Lisina Tehred I.Popovich Proofreader N.Korol: Order 7720/54 Edition 670 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 113035 0 five 0 five 0 five 0 five 0 element And the previous parallel circuit, and the output - with the first input of the second element And the next parallel circuit, the output of the second element And the second parallel circuit is connected to the S-input of the RS flip-flop of this parallel circuit and the R-input of the RS-flip-flop of the first parallel circuit, parallel circuits from the second (M-1) output of the second element I are connected to the S-input of the RS flip-flop of this parallel circuit and to the second input of the second element OR the previous parallel circuit, the second inputs of the second elements AND the parallel circuits from the second to ( M-1) combined and by are connected to the control input of the device and the first input of the control unit, the R input of the RS flip-flop (M-1) of the parallel circuit is connected to the first input of the second OR element (M-2) of the parallel circuit and the second input of the control unit, the third input of which is connected to the output of the SHSh s element (M-1) inputs, the inputs (M-1) of the keys are connected respectively to the inputs of the OR element (M-T) inputs, the combined second inputs of the first SHSh elements (M-1) of the Parallel circuits are connected to output Failure of the control unit. A device according to claim 1, characterized in that, in order to increase the reliability of the control, the control unit contains an OR element, an RS trigger, an AND element, a NOT element and a delay element whose input is connected to the OR element and is the first input of the control unit the output of the delay element is connected to the first input of the AND element, the output of which is connected to the S input of the RS flip-flop, the R input of which is connected to the output of the OR element, the second input of which is the second input of the control unit, the third input of which is NOT connected to the second input the input element And, n my output RS-flip-flop connected to the output control unit Failure.