SU798785A1 - Information output device - Google Patents

Description

restrictions on the relative position and duration of signals in control and information channels. On the other hand, the need to increase the duration of the signal in the control channel reduces the speed of the device, which leads to an increase in the transmission time of information, and this, in turn, reduces the noise immunity and reliability of the device.

The closest in technical terms to this device is a device for transmitting information, containing two triggers, five AND elements, an NOT element, two information inputs, a control unit, two sync pulse buses 2.

A disadvantage of this device is its low noise immunity, since it does not provide protection against interference of different polarities. In this connection, the arrival of low-level interference and, accordingly, the appearance of a permissive signal at the element output at the moment the useful signals arrive at the information inputs of the device, leads to the formation of a spurious signal at the device output. In addition, the duration of the useful signal at the information inputs of the device must exceed the duration of the period of the synchronization signals at the outputs of the control unit, since the synchronization signal from the output of the control unit polls the information inputs of the device, which requires a mandatory coincidence in time of these signals. This, in turn, limits the speed of the device, which leads to an increase in the transmission time of information and to a decrease in the reliability of the device.

The purpose of the invention is to improve the noise immunity and reliability of the device.

The goal is achieved by the fact that the device containing the control unit, the first output of which is connected through the first element AND to the first zero input of the first trigger, the second trigger, the unit and first zero inputs of which are connected respectively to the outputs of the second and third elements AND, the fourth and fifth And elements, the first inputs of which are connected respectively to the first and second information inputs of the device and the element NOT, five triggers are entered, n 1 and 1 elements, the equivalence element and the buffer block, the outputs of which They are a group of information outputs of the device, and the single output of the second trigger is directly connected to the second input of the first element, And, through the sixth element, And to the output

the error signal of the device, and through the seventh And element to the first input of the control unit, the zero output of the second trigger is connected to the first input of the BocbMqro element I, the output connected to the single input of the first trigger, the single output of which is connected to the first input of the second element I, and zero output - with the first input of the third element And, the output of the fourth element And connected with the single input of the third trigger and with the second input of the second element And, the third input of which is connected with the output of the fifth element And with the single input fourth the first trigger, the inputs of the ninth element And are connected respectively to the single output of the third trigger and zero output of the fourth trigger, and the output to the information input of the buffer block, the inputs of the equivalence element are connected to the single and zero outputs of the third and fourth triggers, respectively, and the output directly to the second the input of the seventh element And through the element NOT to the second input of the sixth element And, the first input of the tenth element And is connected to the first control input of the device, and the output to the fourth input ohm second element And a single input of the fifth trigger, the output of which is connected to the second input of the eighth element And, the second input of the control unit is connected to the first input bus clock and the third input of the eighth element And, the fourth input is connected to the output of the sixth trigger, the fifth the input of the second element I is connected to the second bus of clock pulses and to the third input of the control unit, the first input of which is connected to the first control input of the buffer unit, the second output to the second input of the third element I, with one with the second control input of the buffer block, the third output with the first zero inputs of the third, fourth, fifth and sixth triggers, the fourth output with the zero input of the seventh trigger, the fifth output with the third control input of the buffer block , and the sixth output - with the first single input of the seventh trigger, whose single output is connected to the second inputs of the fourth, fifth, and ten elements And, the second single input of the seventh trigger is connected to the second zero inputs of the first sixth trigger, the installation inputs to the state O of the control unit and the buffer unit and with the second control input of the device.

The control unit contains the element AND, the shift register, the first, 65 second and third inputs of which are respectively the first, second third inputs of the block, and the outputs responsibly the first, second, third fifth and sixth outputs of the block, counting the number of characters , the first input is connected to the first input of the block, the second input to the fourth input of the shift register and the installation input to the block O state, and the output to the fifth input of the shift register and the first input of the And element, the second input and output of which are connected respectively to the third and h Four block outputs. In addition, the buffer block contains two registers and a group of elements, whose outputs are the current outputs of the block, and the first inputs are connected to the outputs of the corresponding bits of the first register, the first and second inputs of which are connected respectively to the information and the first control inputs of the block the outputs of the corresponding bits are with the group of inputs of the second register, the group of inputs with the group of outputs of the second register, the first input connected to the second control input of the block, and the second input to the third input of the first register and input for setting a state of O unit. The drawing shows a block diagram of the device. The device for retrieving information contains triggers 1-7, control block 8, AND elements 9-18, equivalence element 19, buffer output block 20, HE element 21, first 22 and second 23 information inputs of the device, first 24 and second 25 control device inputs, control module B 2631 outputs, input buses 32 and 33 clock pulses, device information output 34, device error signal output 35. The control block 8 contains the shift register 36, the number of characters counter 37 and the AND 38 element. The equivalence element 19 contains AND 39 elements and the OR 40 element. The output block 20 contains registers 41, 42 and And group 43 elements, the number of which is equal to the number of bits in register 41. The device operates as follows. In the initial state, all the device triggers that can be executed, for example, in the basis of the AND-OR-NOT element, are in the state O. Before transmitting information to the device input 25, a reset signal is received, which sets the state to 1 trigger 7, confirms the state of the flip-flops 1-6 of the block 8, the output block 20, and thereby prepares the elements 12, 13, 18 for the passage of signals. After that, the input 22 receives a signal corresponding to code 1 of the transmitted information signal. In the case of transmission of the code O, the information signal is respectively transmitted only to the input 23. Simultaneously with the signal arriving at the first or second information inputs of the device, the clock signal accompanying each character of the transmitted information arrives at the input 24. With the arrival of code 1 in the transmitted information symbol, the triggers 3 and 5 are set to state 1, and a signal is formed at the output of the AND element 17, since both of its inputs are prepared. The signal from the output of the element And 17 is fed to the information input of the output block 20 and further to the output of the register 41. Registers 41, 42 are designed to convert the incoming serial code into parallel, and the elements 43 to transmit the parallel code on the outputs 34 to any external subscriber, for example, a storage device. When trigger 5 is set to state 1, element 16 is fully prepared, since triters 2 and b are in state 0 and signals from their zero outputs prepare the corresponding inputs of element 16. Another sync pulse arriving on the bus 32 is shifted relative to the sync pulse arriving at the bus 33, for half the following period, passes through the element AND 16 to the single input of the trigger 1 and sets it to the state 1. The signals from its single output prepare the element 10, through which the signal The bus 33 begins only after the falling edge of the clock signal arriving at input 24 and the trailing edge of the information signal entering input 22. After the falling edge of the indicated signals, at the outputs of the elements 12 and 18, the enabling signal appears and Thus, element 10 is prepared through which a regular sync pulse from bus 33 passes to a single input of trigger 2. If the signal to input 22 at input 23 does not receive a false signal, then the triggers 3 and 4 are in opposite states. Due to the fact that the inputs of one of the elements 39 of the equivalence element 19 are connected to the zero outputs of the flip-flops 3, 4, and the inputs of the other element 39 are connected to the single outputs of the same triggers, then at opposite states of the flip-flops 3 and 4 the signal at the output of the equivalence element 19 becomes resolving for element 15. Since element 15 is prepared, the signal from the single output of flip-flop 2 passes to the first input of block 8, and to output 35 of the error signal through element 14 does not pass, since the latter is closed by the authorization signal from the exit ale NOT 21. From the threshold output of the block 8, the signal arrives respectively at the input of the shift register 36, after which the formation of signals at its outputs and accordingly at the outputs 26, 27, 28 of the block 8 begins. Simultaneously from the output of the element 15, the signal arrives at the input of the counter 37 intended for fixing the moment of the end of a given number of symbols of information. The signal at output 26 of block 8, generated synchronously with the sync pulse on bus 32, arrives at the first input of element AND 9 and passes to the first zero input of trigger 1, because element AND 9 is prepared by a signal from the unit output of trigger 2. When the trigger 1 is set to state O, the element 11 is prepared, and the second signal generated at the output 27 of the block 8 synchronously with the sync pulse on the bus 33 passes through the element 11 to the first zero input of the trigger 2 to reset it. Simultaneously with setting the trigger 2 to the state O of the signals from the output 27 of the block 8, the state is set to the state 1 of the trigger b, the signal from the zero output of which closes the element I 16. In this connection, the re-installation to the state 1 of the trigger 1 is excluded and, consequently, the restart of block 8, if by this time point the signal at input 25 is still present. In addition, the signals from the outputs 26, 27 are fed to the control inputs of the output block 20 and further to the inputs of the registers 41, 42 for code conversion.

The code conversion in the output block 20 is performed as follows.

When a signal from output 26 enters the first bit of register 41, a code is inputted to the information input of output unit 20 from output element I 17, and from second to Mth bit, the code from register 42, which has one less than register 41. When a signal from output 27 arrives at the first digit of register 42, the code from the first register register 41 is entered, and the M-th register register 42 receives the code from M-1 register bit 41. The signal formed at the output 28, the triggers 3-6 are set to the state O, thereby completing the cycle of receiving one sim ol information. The delay in the formation of the signal at the output 28 of the block 8 is chosen so that the reset of the triggers 3-6 occurs after the end of the transients

which are possible with the falling edge of the input signals due to the influence of the communication line connected to the information inputs 22, 23 and to the control input 24 of the device. This eliminates the influence of interference generated during the falling edge of the input signals on the operation of the device.

Functioning device nodes

 when transmitting the code O is carried out in a similar way, the input signals are fed to the inputs 23 and 24 of the device, and then to the inputs of the flip-flops 4 and 5, respectively. The signal from the single output of the flip-flop 5 through the element

5 and 16 performs the setup in state 1 of flip-flop 1, the signal from the single output of which, in turn. results in setting to state 1-trigger 2 and starting control block 8. At outputs 26-28 of block 8, the formation of the next group of synchronization signals begins again, and the cycle of operation of the device is repeated. After receiving a group of information symbols, for example, a corresponding control or information word transmitted from a digital computer, a signal is generated at the output of the counter 37, which allows the formation of a group of signals at the outputs 29, 30, 31 of block 8.

 The signal generated at the output 29 synchronously with the signal at the output 28 sets the trigger 7 to the state O and thus prohibits the input of signals to the single inputs of the triggers 3, 4 and 5 from the inputs 22, 23 and

24 devices, respectively. The second signal, generated at the output 30, transmits the code from the register 41 through the elements 43 to the output

0 34, and the third signal from output 31 sets the trigger 7 to state 1 to prepare the device for receiving the next group of input information symbols.

5, if at the moment the pulse arrives at the input 22, a signal of interference arrives at the input 23, then both flip-flops 3 and 4 appear in state 1, as a result of which a signal is generated at the output of the equivalence element 19 that prevents the signal from the single output trigger 2 through the element And 15 to start block 8. The same signal

- from the output of the equivalence element 19 arriving at the input of the element HE 21, the signal is allowed to flow from the single output of trigger 2 through the element 14 to the output 35. The error signal is used, for example, for

0 build transmission. In this case, input 25 receives a reset signal, which sets in state 1 a trigger 7 and confirms the state O of all other nodes of the device. Then the information transfer cycle begins, as described above.

If an interference signal is generated at device input 24 in the absence of signals at inputs 22 and 23, then both flip-flops 3 and 4 remain in state O, and a inhibitory signal is also generated at the output of equivalence element 19, which in turn leads to the formation of a signal output 35 of the error signal. With the simultaneous influence of interference signals on the inputs 22, 23 and 24, the transfer to the outputs 34 of the device of a false code is also excluded. In this case, a signal is generated at output 35 and the launch of block 8 is prohibited. If a signal of interference is possible at the time of forming signals at inputs 22, 23, which leads, for example, to a short-term loss of useful signals, in this case false positives are also excluded. information to the outputs 34, since the signal from the output 28 sets the state O of the flip-flops 35 with a delay after the falling edge of the input signals. The moment of formation of the signal at the output 28 in this case is chosen taking into account the duration of the input signals and the duration of the transient processes possible after the falling edge of the input signals, since the start of block 8 may occur at the moment of short-term decrease of useful signals.

Thus, in comparison with the known device, the device eliminates the transmission of false information to the device outputs when incoming information signals and the control input of the device receive interference signals of any polarity, which is possible, for example, when simultaneously exposed to strong electromagnetic fields, on communication lines connected to the inputs of the device. This is achieved by detecting the input to the device inputs of erroneous information in the intervals between the transmission times of symbols of the same group. In addition, in the time interval equal to the duration of the formation of useful signals at the inputs of the device, as well as in the time interval after the falling edge of the input signals until the input triggers 3-5 are reset and between the transmission times of two neighboring groups of information symbols, complete elimination is achieved arrivals at the inputs of triggers 3-5 interference signals. This increases the noise immunity, and hence the reliability of the device.

The proposed device also has broader functionality, since it is intended to transmit both a number of pulse code and any other code, for example, a position code.

In addition, since the launch of the basic information generation units of the trigger 2, the control unit 8 and the output device 20 occurs after the falling edges of the input signals, the device is not critical to the duration of the input signals. This expands the functionality of the device, as well as its speed, which, in turn, increases the noise immunity and reliability of the device due to the possibility of reducing the time for receiving information.

Claims (3)

1. A device for outputting information, containing its control unit, the first output of which is connected via the first element I to the first zero input of the first trigger, the second trigger, the unit and the first zero 5 whose inputs are connected respectively to the outputs of the second and third elements And, the fourth and fifth elements And, the first inputs of which are connected respectively to the first and second 0 informational inputs of the device and a NOT element, characterized in that, in order to improve the noise immunity of the device, five triggers, five AND elements, an equivalence element and a buffer block, whose outputs are a group of information outputs of the device, are entered into it; a single output of the second trigger is directly connected to the second input of the first 0 elements And, through the sixth element And - with the output of the device error signal, and through the seventh element And with the first input of the control unit, the zero output of the second trigger is connected to the first input of the eighth element And, the output connected to the single input of the first trigger, the unit output of which is connected to the first input of the second element , and the left output is with the first input of the third element I, the output of the fourth element I is connected to the single input of the third trigger and to the second input of the second element and whose third input is connected to the output n 5 of that element I and E inichnym input of the fourth flip-flop input of a ninth AND gate connected respectively with the output of the third trigger unit, and the zero output of the fourth flip-flop, and an output - a data input buffer unit, equivalence inputs connected Accordingly element with unit and zero outputs of the third and fourth flip-flops, 5 and the output - directly from the second the input of the seventh element I and through the element NOT to the second input of the sixth element I, the first input of the tenth element I connected to the first control input of the device, and the output to the fourth input of the second element I and the single input of the fifth trigger, the output of which is connected to the second the input of the eighth element And, the second input of the control unit is connected to the first input bus of clock pulses and the third input of the eighth element And, the fourth input of which is connected to the output of the sixth trigger, the fifth input of the second element And is connected to the second sync pulses with the third input of the control unit whose first input is connected to the first control input of the buffer block, the second output to the second input of the third buffer element I, to the single input of the sixth trigger and to the second control input of the buffer block, the third output to the first the zero inputs of the third, fourth, fifth, and sixth flip-flops, the fourth output — with zero input of the seventh flip-flop, the fifth output — with the third control input of the buffer block, and the sixth output — with the first unit input of the seventh flip-flop whose single output is connected to the second inputs of the fourth, fifth, and ten elements And, the second single input of the seventh trigger is connected to the second zero inputs of the first sixth triggers, to the installation inputs to the control unit O and the buffer block and to the second control input devices. 2. The device according to claim 1, characterized in that the control unit contains an element AND, a shift register, the first, second and third inputs of which are respectively the first, second and third inputs of the block, and the outputs are respectively the first, second, third, n the fifth and sixth inputs of the block, a counter of the number of characters, the first input connected to the first input of the block, the second input to the fourth input of the shift register and the installation input to the O state of the block, and the output to the fifth input of the shift register and the first input of the And element, the second the input and output of which is connected here, respectively, with the third and fourth outputs of the block. 3. The device according to claim 1, characterized in that the buffer block contains two registers and a group of elements, whose outputs are the corresponding outputs of the block, and the first inputs are connected to the outputs of the corresponding bits of the first register, the first and second inputs of which are connected respectively to the information and the first control inputs of the block, the outputs of the corresponding bit bits — with the group of inputs of the second register, the group of inputs — with the group of outputs of the second register, the first input connected to the second control input of the block, and the second input - with the third input of the first register and the input of the installation in the state of the block. Sources of information taken into account in the examination 1. USSR author's certificate number 414585 ... class. G 06 F 3/04, 1971. 2. USSR author's certificate No. 306554, cl. H 03 K 3/28, 1969 (Pro 4Q Totip).