SU1596477A1 - Device for receiving bi-pulse signals - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to increase throughput. The device for receiving bi-pulse signals contains differentiating blocks 1 and 2, trigger 3, delay blocks 4 and 5, waiting for multivibrators 6 and 7, elements AND 8-11, registers 12 and 13, and a decoder 14. The goal is achieved by eliminating the incorrect sync pulse, which occurs when the boundaries of the transmitted message are selected, as well as when there is an error in the received data. 1 il.

Description

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The disclaimer relates to communication technology and can be used in data transmission systems that use self-timed codes.

The purpose of the invention is to increase throughput.

The drawing shows a structural electrical circuit of the proposed device. .

The device contains the second, the first differentiating blocks 1,2, the trigger 3, the first 4 and the second 5 blocks of the delay, the first 6 and the SECOND 7 standby multivibrators, the first 8, the second 9,

third 10, fourth 11 elements And, the first 12 and second 13 registers, the decoder 14.

. The device works as follows.

With the help of differentiating unit 1, the pulse fronts of received biim | puls signals are differentiated (assuming that biopulse parcels reconstructed in duration and amplitude arrive at the input device). As a result, a sequence of differentiation pulses is formed at its output, from which using trigger 3 and block 4 (its delay is 0.75T, where T is the period of bi-pulse signals), only periodic impulses allocated in the middle of the bi-pulse signal are selected. . By differentiating the leading edges of periodic pulses coming from the direct output trigger 3, a sequence of synchronizing pulses is generated at the output of differentiating unit 2. According to the SI, depending on the value of the pulse in the first half of the bi-pulse signal, the binary signal is recorded into the register 12.

To delimit the transmitted message (cycle synchronization, the last bit of the message, depending on its binary value, encodes a pair of 0 (1) (11) characters of the same name, i.e., the code structure is violated, which leads to the absence of a differentiation pulse in the middle of the bi-pulse The absence of a pulse is determined by block 5, which delays by 0.5 T pulses generated at the direct output trigger

3, and element 8. The coincidence of pulses at both inputs of element 8 is possible only if a periodic differentiation pulse is missed as a result of trigger 3 being in a single state by more than 0.25 tons. If there is no violation of the code structure, such a situation cannot occur. For a single signal from the output of the AND 8 element, the standby multivibrator 6 generates a single pulse, the duration of which is 0.5T. This impulse coming from the inverse output of the standby multivibrator prohibits the passage through element 9 of the input to the installation of the non-periodic impulse of differentiation of the SR in the zero state of the trigger 3, which eliminates the violation of the correctness of the emission of the SR. A positive voltage drop generated on the inverse output; a second torch is launched, which forms a single pulse, with a duration of .0.25 tons, used to restore the missed pulse. The differentiating unit 2 is used to form short SIs. The elimination of the possibility of false phasing is provided in the device using a register 13 and a decoder 14.

Claims (1)

During normal operation of the device (there are no errors in the received data) in register 13, when a synchronizing pulse arrives, a unit is sequentially shifted (a single signal is recorded in one of the bits of register 13, and zero is written in the others). The register size 13 is chosen equal to the length of the message (n). The unit shifts synchronously with the reception of symbols, and the number of the received message symbol corresponds to the register bit number 13. Thus, when receiving the last (n - th) message symbol, a single signal appears at the nth output of register 13, which determines the location receiving tags. During normal operation of the device, single signals generated at the direct output of the waiting multivibrator 6 and nm coincide; register 13 is output. The presence of a signal at the output of the And 11 element means the common-mode operation of the device. This signal is synchronized with the arrival of the first character of the new message in the first bit of register 13, a single character is written. By the information consumer, the signals received from the output of the And 11 element are used to read information by a parallel code from the register 12. When an error is received, the device operates as follows. The presence of an error in the received data also leads to a disruption of the bi-pulse code structure, which leads to a missing clock pulse (errors leading to a change in the values in the bi-pulse signal are not considered. Due to the low probability of their occurrence in the fiber-optic line communication). When a distorted symbol (error) is received, a signal is generated at the output of the waiting multibirator 6, which does not coincide with the label arrival time, as a result of which a signal appears at the output of AND 10 that detects the presence and location of the error in the received message. By this signal, a single (zero) symbol is recorded in the information bit in the information consumer and corrected (one-time errors are corrected either by hardware or software, and when errors occur, the message is re-asked or eliminated). In case of distortion of the mark (non-gap) or synphasic disorder, the receiving device works as follows. At the time of the arrival of the high uranium signal from the nth output of the register 13 to the first input of element 11, the second input of this element does not receive a signal from the direct output of the waiting multivibrator 6, which determines the arrival of the label, as a result of which a single character is overwritten in the first digit of the register 13, t, e. the moment comes when zeros are written in all bits of this register. This state of register 13 is allocated by means of a decoder 14, the signal from the output of which records units (single characters) to all bits of register 13. When receiving data, in this case, as before, the register 13 is shifted combinations, however, single signals that are not acknowledged by the tag reception signal are erased by AND 11, and their place in the corresponding bit of register 13 is written to the zero character. Due to the low probability of symbol distortion in fiber-optic communication lines (10,, ,,, 10-), the device during reception of one message is guaranteed to enter the in-phase operation, t, e, in register 13 by the time it receives another tags, there is only one unit character (in the nth size), which will coincide with the time of its arrival. The signal from the output of the decoder 14 makes a conclusion about the loss of the synchrophase operation of the device (the message is eliminated with possible subsequent reshoot), and upon subsequent receipt of the signal from the output of the And 11 element, the information consumer concludes that the device enters the common-mode operation. To ensure normal operation of the device at the initial moment of time or when operating in start-stop mode, a zero symbol must be transmitted at the beginning of the data (this ensures the right timing of the clock), Formula of the Invention Device for receiving bi-pulse signals containing a trigger, the inverse output of which is connected through the first delay unit with its first input, the second delay unit, the first and second elements And, the first and second waiting multibirators and the first shift register, which is different from the fact that The first and second differentials are introduced; the operating units, the third and fourth And elements, the second shift register and the decoder, with the direct trigger output connected to the second differentiating unit input, the first input of the first And element, and through the second unit the delays with its second input, the input of the second differentiating unit and the first input of the first shift register are the input of the device, the output of the second differentiating unit is connected to the first input of the second element I, the output and the second input of which connect respectively with the second trigger input and the inverse output of the first standby multivibrator, the input of which is connected to the output of the first element And, and the direct output with the first inputs of the third and fourth elements And, the outputs of which are the first and second outputs of the device, the inverse output of the first waiting through the second standby multivibrator is connected to the second input of the second differentiating unit, the output of which is connected to the first input of the second shift register and the second input of the first shift register; The orodes are information codes of the device, the signals of the fourth element, and are connected to the second input of the second shift register, the outputs of which are connected to the inputs of the decoder, the last output of the second shift register is connected to the second inputs of the third and fourth elements, -; This is the third output of the device.