SU1631741A1 - Cyclic phasing device for optical fiber data pransmission systems - Google Patents

Abstract

The invention relates to telecommunications and can be used in information transmission systems with self-synchronizing codes and, in particular, in fiber-optical information transmission systems. The aim of the invention is to increase speed. For the organization of frame synchronization, the obligatory presence of a pair of pulses of the type 10 (01) in the last (nth) bit of the message is used. In the case when the indicated pair of pulses should not occur in the nth bit in accordance with the incoming sequence of binary symbols, the code structure is violated, which ensures the presence of a change in the pulse values in the nth bi-pulse interval. In this case, for the organization of cyclic phasing is not provided for the introduction of redundant characters. The cyclic phasing device for fiber-optic information transmission systems contains a shift register 1, a pulse generator 2, a counting trigger 3, a pulse counter 4, first and second differentiating units 5 and 6, delay line 7, element OR 8, additional element OR 9, first , second and third elements And 10-12, additional element And 13. 2 ill. (L

Description

The invention relates to telecommunications and can be used in information transmission systems with self-synchronizing codes, in particular in fiber-optic information transmission systems.

The aim of the invention is to increase performance.

On Fig, 1 presents a structural electrical diagram of a cyclic phasing device for fiber optic information transmission systems; figure 2 - timing diagrams of signals explaining the operation of the cyclic phasing device for fiber-optic information transmission systems. tion

The cyclic phasing device for fiber-optic information transmission systems contains shift register 1, pulse generator 2, counting trigger 3, pulse counter 4, first and second differentiating units 5 and 6, delay line 7, element OR 8, additional element OR 9, first , the second and third elements And 10-12, an additional element And 13,

The cyclic phasing device for fiber-optic information transmission systems operates as follows.

Conversion of the transmitted data from binary to bi-pulse is as follows.

The message from the information source by the parallel code is written into the shift register 1 (from the first to the nth digits, Fig. 1), which serves to convert the parallel data format to serial (Fig, 2a). The data shift is carried out by clock pulses (CH) j coming from the output of the first differentiating block 5 (fig.2d). By differentiating the packages at the output of the second differentiating unit 6 (Fig.2b) ', a sequence of pulses is formed corresponding to the moments of the change of values in the transmitted symbols. Since the change of symbol values is represented by the presence of a transition in the bi-pulse signal (Fig. 2a), using the delay line 7, these pulses are delayed by 1/2 Τ (T is the period of the bi-pulse signals in Fig. 2g). Pulses of changing the values of the pulses and pulses marking the boundaries of the bi-pulse packets (Fig.2d), come from the output of the first differentiating unit 5, highlighting the leading edges of the clock pulses (Fig.2c), generated by the generator 2, are combined using an additional element OR 9, the output of which the pulse train (Fig. 2e) is supplied to the counting input of the counting trigger 3 and sequentially changes its state (Fig. 2g), as a result of which a data sequence is generated at the output of the counting trigger 3, p edstavlennyh in biimpulsnom code.

Labeling is carried out as follows.

At the moment of arrival of the ηth message symbol (they are calculated by SI using counter 4), a single signal is generated at the output of counter 4 (Fig.2z), according to which the following operations are performed: it is forbidden to pass differentiation pulses from the output of the perforated through an additional element And 13 differentiating block 5; using the first and third elements And 10, 12 the analysis of the values of the characters in the p-th and n-1-m characters (figa, b, d). If their values are opposite (i.e., the presence of a pulse change in the middle of the ηth bit will occur naturally), then a single signal is formed at the output of the third element And 1 2 (it replaces the signal from the output of the additional element And 13). When these symbols have the same binary value (figa), i.e. at this moment in time, there is no differentiation pulse at the output of the second differentiating block 6, a single signal (Fig.2i) is formed at the output of the first element And 10, which, after holding it at 1/2 T, changes the polarity of the pulses in the ηth bit, due to the exception in this beat of the differentiation pulse from the output of the first differentiating block 5, marking the boundaries of the bi-pulse signals, a violation of the code structure occurs (Fig.2g); according to the pulse formed in the second half of the nth bit, the next message is recorded from the information source, which corresponds to the beginning of a new cycle of operation of the cyclic phasing device for fiber-optic information transmission systems (Fig.2k).

The initial installation ^{of the} cyclic phasing device ¹ for fiber-optic information transmission systems (the moment of initial switching on) is ensured by resetting the state of the counting trigger 3 and the counter 4.

Claims (1)

SUMMARY OF THE INVENTION A cyclic phasing device for fiber optic information transmission systems comprising a pulse generator, a first element AND and an OR element, a second element And and a shift register connected in series, as well as a third element And, a counting trigger and a pulse counter, inputs of the shift register, the combined installation inputs of the counting trigger and the pulse counter and the output of the second element And are respectively information inputs, the installation input and a control output of the device, characterized in that, in order to improve performance, a first differentiating unit, an additional AND element and an additional OR element, the output of which is connected 5 to the counting input of the counting trigger, as well as a second differentiating unit and a delay line, are introduced this input and output of the delay line are connected respectively to the output of the OR element 10 and the second input of the additional OR element, the output of the pulse generator is connected to the first input of the third AND element, the input of the second element And and the counting input of the pulse counter, 15 the output of which is connected to other inputs of the second element And and the additional element And and the second inputs of the first and third elements And, the third inputs of which, combined 20 with the clock input of the shift register, are connected to the output of the first differentiating unit, the fourth inputs of the first and third elements AND combined with another input of the OR element 25 are connected to the output of the second differentiating block, the input of which is connected to the output of the shift register, and the output of the third element The AND element is connected to the third input of an additional OR element, and the output of the counting trigger is the information output of the device. Figure 2