SU1728975A1 - Channel selector - Google Patents

Abstract

The invention relates to telecommunications and can be used in computing devices, telemechanics, receiving equipment of communication means, where. information is entered from several sources. The purpose of the invention is to improve the speed of the device by using the asynchronous principle of operation. The channel selection device contains the element NOT, the first trigger, the clock generator, the binary counter, the decoder, the second trigger and the channels. Each channel contains a signal conversion unit, the first and second AND elements, a trigger, the NOT element, the first and second OR elements, a parallel shift register with a three-stage output, and a channel number code generator with a three-stage output. In this device, more high-speed performance is provided by the asynchronous principle of operation. 1 il.

Description

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The invention relates to telecommunications and can be used in computing equipment, telemechanics, receiving equipment of communication facilities, where information is entered from several sources.

The aim of the invention is to improve the speed of the device.

The drawing shows a functional diagram of the device channel selection.

The channel selection device contains the element He 1, trigger 2, generator 3 clock pulses, binary counter 4, decoder 5, trigger 6 and channels, each of which contains a signal conversion unit 7, register 8 s. three-stable output, the first element And 9, the trigger 10, the second element And 11, the element NOT 12 with open collector output, the first element OR 13, the generator 14 of the code of the channel number with

three-stable output and the second element OR 15.

The device works as follows.

The circuit connecting the fourth channel inputs performs the function of the inhibit circuit, through which channel blocking occurs, and the function of the control circuit trigger circuit performed on elements 1-6, the signal sources of this circuit are NOT 12 channels, and the consumers are elements And 9 channels and the element is NOT 1.

The device allows you to receive information parcels, presented in a sequential code, from several lines, convert them into a parallel code and then output them in turn, for example, to a computer, accompanied by a strobe and a channel number code from which

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information package. The sequential input of codes is accomplished by blocking the triggers of the 10 remaining channels for the duration of entering the code from the channel that was triggered first. When two or more channels are triggered at the same time, the device resets the triggers of all triggered channels, except for the very first in the chain from the group of triggered ones.

When a data message is received through one of the channels (to the first input of the channel), a signal appears on the second output of the signal conversion unit 7 that triggers trigger 10 through the open element I 9. A single signal passed through the output of trigger 10 with open collector output 12 and inverted closes the elements AND

9 in all channels, and in addition, trigger 1 is not activated by element 1. Trigger 2 enables the generator 3 clock pulses, as a result of which counter 4 begins to count, the code changes at its output, and pulses appear at output 4 of the decoder 5: after the first clock cycle, the pulse at the second output, after the second pulse, at the second output will disappear, and at the third clock, etc. With this pulse distributor (elements 3-5), a time diagram of the operation of the device is formed. So, after the first clock cycle, the signal from the second output of the decoder 5 will trigger trigger 6, the signal from the output of which through the channel element 11 will allow to transmit the code from the signal conversion unit 7 to the register 8, allow issuing the information code and the channel number code to the device output, as well will reset the signal at the second output of conversion unit 7. In this case, the information code and the channel number code will be present at the output of the device up to the third clock cycle, i.e. until the trigger 6 is reset by the signal from the fourth output of the decoder 5. During the time while the trigger 6 is in the cocked state, the signal from the third output of the decoder 5 will pass to the output of the device. This signal acts as a strobe, and according to this signal, the information code and the channel number code will be read into a subsequent device (for example, in a computer).

In case of simultaneous arrival of parcels through two or more channels at once and simultaneous charging of triggers 10 triggers

The 10 channels having a lower priority are dropped by the signal from the second output of the most priority channel through the chain through elements 13 and 15. In any case, the loss of information is excluded,

since the code that arrives on any of the channels is saved in block 7 of the signal conversion of the corresponding channel until it is read.

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A channel selection device containing a counter, a first trigger, a second trigger connected in series and a clock generator, and each channel contains a first AND element, a trigger and a shift register, the first inputs of the channels being inputs to the device, the first output of which is the first output of the first channel , characterized by

5 that, in order to improve speed, the decoder and the element are NOT, and in each channel is a signal conversion unit, the first and second elements OR the element NOT, the second element AND and the code generator of the channel, while the output of the element is NOT connected to the first input the second trigger, the output of the clock generator is connected to the counter input of the counter, the outputs of which are connected to the inputs of the decoder, one outputs of which are connected to the first and second inputs of the first trigger and to the second input of the second trigger, which is also connected to the mouth novochnym counter input and the second input channels, output

0 of the first trigger is connected to the third inputs of the channels, the fourth inputs of which are connected to the input of the element NOT. the second output of each channel is connected to the fifth input of each subsequent channel, the first and

5, the third outputs of all channels are combined, the third output of the first channel and the other output of the decoder are respectively the second and third outputs of the device, with each channel having information and

0 control outputs of the signal conversion unit are connected respectively to the information input of the shift register and to the first input of the first element AND, the output of which is connected to the first input of the trigger, the output of which is connected to the first input of the first element OR, the input of the element NOT and the first input of the second element AND The output of which is connected to the input of the generator of the code of the channel number, to the control

0 to the input of the signal conversion unit, the synchronizing input and the resolution enable input of the shift register code, the setup input of which is connected to the first input of the second OR element, the second input and output

5 which is connected respectively to the second inputs of the first OR element and the trigger, the output of the element is NOT connected to the second input of the first element AND and is the fourth input of the channel, the first, second, third and fifth inputs and the first, second

and the third outputs of which are co-elements AND, the second input of the second element

responsibly, the information input of the OR block, the output of the shift register, the output of the signal transducer, the first input of the second OR element, and the output of the code generator

element OR, the second input of the channel number monitor.

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Claims (1)

Claim A channel selection device comprising a counter, a first trigger, a second trigger and a clock generator connected in series, and each channel containing a first AND element, a trigger and a shift register, the first channel inputs being device inputs, the first output of which is the first output of the first channel, characterized in that, in order to improve performance, a decoder and a NOT element are introduced, and a signal conversion unit, the first and second elements OR, an NOT element, a second AND element and a code generator channel number are entered into each channel la, while the output of the element is NOT connected to the first input of the second trigger, the output of the clock generator is connected to the counting input of the counter, the outputs of which are connected to the inputs of the decoder, one of which outputs are connected to the first and second inputs of the first trigger and to the second input of the second trigger, which also connected to the installation input of the counter and the second inputs of the channels, the output of the first trigger is connected to the third inputs of the channels, the fourth inputs of which are connected to the input of the element NOT. the second output of each channel is connected to the fifth input of each subsequent channel, the first and third outputs of all channels are combined, the third output of the first channel and the other output of the decoder are respectively the second and third outputs of the device, and in each channel the information and control outputs of the signal conversion unit are connected respectively to information input of the shift register and to the first input of the first AND element, the output of which is connected to the first input of the trigger, the output of which is connected to the first input of the first OR element, the input of the NOT element and the first input of the second AND element, the output of which is connected to the input of the channel number code generator, to the control input of the signal conversion unit, the synchronizing input and enable input of the shift register code, the installation input of which is connected to the first input of the second OR element , the second input and output of which are connected respectively to the second inputs of the first OR element and trigger, the output of the element is NOT connected to the second input of the first AND element and is the fourth channel input, the first the second, third and fifth inputs and the first, second and third outputs of which are respectively the information input of the signal conversion unit, the first input of the second OR element, the second input of the second AND element, the second input of the second OR element, the shift register output, the output of the first OR element and the output channel number code generator.