SU1753605A1 - Device for reception of information in fiber- optical communication lines - Google Patents

Abstract

The invention relates to a communication technique and can be used in data transmission systems using synchronized codes, in particular in fiber optic information transmission systems. The aim of the invention is to reduce the phasing time. Fourth, fifth, and sixth elements 17, 15, 16, decoder 19, counter 11, fifth trigger 7, and element OR 18 are entered into the device. When violations occur when one message is received, the device goes into a phasing mode and performs a frame adjustment at receiving the next message label, as a result of which the implementation of the frame synchronization mode is provided for the reception of a single message. 2 ill., 2 tab.

Description

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The invention relates to communication technology and can be used in data transmission systems using synchronization codes, in particular in fiber-optical information transmission systems,

The purpose of the invention is to reduce the phasing time.

Fig, 1 shows a block diagram of the device; Fig. 2 shows voltage plots explaining the operation of the device.

The device contains a shift register 1, the differentiating unit 2, the first to the fifth triggers 3-7, the first 8 and the second 9 delay lines, the driver 10 pulses, the counter 11 pulses, the first to the sixth elements And 12-17, the element OR 18, decoder 19.

The elements of the device are connected as follows. The device input is connected to the information input of the shift register 1, the outputs of which are the information outputs of the device, and through the pulse shaper 2 with the installation input into the single state of the first trigger 3, the inverse output of which through the second delay unit 9 is connected to its installation input into the single state, direct output - to the clock input of the register 1 shift the input of the pulse former, the output of which is connected to the counting input of the pulse counter 11, the first inputs of the first, second, third, fifth, sixth The elements And 12, 13, 14, 16 and 17, the synchronous inputs of the second, third, fourth triggers 4, 5 and b and the input of the first block 8 of the delay, the first to fifth outputs of which are connected to the second inputs of the first, second, third, respectively And 12. And 13th elements. 13, 14, 16, 17, the outputs of which are connected respectively to the first through fifth inputs of the decoder 19, the sixth input of which is connected to the output of the counter 11 pulses, and the seventh, eighth and ninth inputs to the forward the outputs, respectively, of the second, third, p of those triggers 4, 5, 6, informational inputs to which are connected respectively to the third, fourth and fifth outputs of the decoder 19, the first output of which is connected to the first installation input of the pulse counter 11, the first input of the fourth element And 14 and the installation input to the zero state of the fifth trigger 7, and the second output to the first the input element OR 18 to the second input of which receives the signal of the initial installation, and the output is connected to the installation input to the unit state of the fifth trigger 7, the direct output of which is connected to the second installation input of the pulse counter 11, and clear - to the second input of the fourth element I 14, with the fifth output of the decoder 19, the direct outputs of the second, third and fourth triggers 4, 5 and b and the output of the fourth element

And 14 are control outputs of the device.

The device works as follows (an explanation of the operation of the device is carried out using diagrams

0 voltages shown in FIG. 2).

In order to ensure normal operation, the initial setup (NU) of the device elements is carried out. On this signal, the first, fifth triggers 3, 7 are set to one, and the second, third, fourth triggers 4, 5, b are set to zero (on some links are not indicated in the block diagram in order to simplify it). High level signal with

0 direct output of the fifth trigger 7 sets and holds the pulse counter 11 in a state in which a single signal will be output (corresponds to the moment of reception of the first

5 message symbols) until the label is selected as part of the received data (it is transmitted in the first bit of the message), the received message is thus framed with labels (first, the label of this message, characterizing the type of message received after it, and at the end of the next message). message), while issuing a frame alignment signal for issuing the received communication to the consumer occurs by the next message label (it records the time when the message was received), and it is believed that during data transmissions x cannot follow another message of the same type.

0 At the initial moment of time, the device operates as follows. A sequence of bi-pulse signals is received at the device input (Fig. 2a), and to ensure the minimum connection update time (joining the communication), it is necessary that the zero character ( the start of the device is ensured by a differentiation pulse, selected in the middle of the bi-pulse signal). However, this condition is not necessary, since the first change in the value of the received bi-pulse signals will restore the correct operation of the device. Via

5 differentiating key 2, the first trigger 3 and the second delay block 9 (the delay time of which is 0.75 T, where the T-period of the bi-pulse signals) is extracted from the received data SI (Fig 2 in)

the front of these pulses is written to the first shift register 1 of the data represented in binary form (Fig. 2 g). The start bit is then skipped. On the falling edge of the SR, a generator of 10 pulses is started, at the output of which short control pulses are formed (Fig. 2e), arriving at the counting input of the pulse counter 11, to the input of the first delay block 8, at the first output of which pulses appear with a delay T -1/2 D g; on the second - T; on the third - T + 1/2 Ar; on the fourth T-Dti on p volume T + Dg. These pulses come to the second inputs of the first, second, third, fifth, sixth elements And 12, 13, 14, 16, 17, and at the output of the first element And 12 a single signal is formed when the SI delay value is -1 / 2G; at the output of the second element And 13 - at +1/2 Dg; at the output of the third element And 14 - at 0 Dg; at the output of the fifth element And 15 - at-Dg and at the output of the sixth element OR 16 - at + Dg. Moreover, when receiving the first character of the next message, the SI shift value is (Dti - Dc) / 2, where And and i, respectively, the SI shift value upon receipt of the previous and current message types (averaging is performed because the delay is measured with respect to only one clock cycle). Obviously, in this case, the value of the SI offset will depend on the previous and current type of received messages.

In tab. Figure 1 shows the offset values depending on the types of received messages. In this table, the symbols 1-1 and i denote the receive cycles, and the letters B, H, and M denote the symbols large (first type of message), normal (second type of message), and short duration (third type of messages), respectively.

As can be seen from the table. 1 and FIG. 2e-n, when receiving characters of one message, the value of the SI shift is constant and depends on the type of message (from -D to + Dt), when receiving the first character of the message, it depends on the previous type of message and varies from -1/2 Dg to +1 / 2 D g. These differences are used to highlight the moment of reception of the first character, i.e. extracting the frame alignment signal (CA), and validating the reception of message symbols,

In order to isolate the SI shift moment and identify the SI shift value, the first delay unit 8, the decoder 20 and the first, second, third, fifth, sixth elements And 12, 13, 14, 16, 17 are used.

The logic of the formation of control signals at the outputs of the decoder 20 is given in Table. 2 and is explained with reference to the stresses shown in FIG.

2nd-n.

After the initial installation, symbols of constant (normal) duration arrive at the device input. Until the moment of changing message types is highlighted

0, the counter 11 is held by the first flip-flop 7 in the initial state, as a result of which a high level signal will be permanently outputted at its output (the fixing time of reception of the first character

5 messages from which the tag is extracted. At the output of the third element I 14, when receiving pulses of normal duration (OD t), a single impulse will be generated, according to which from the third output of the decoder 19 the third trigger 5 (it records the reception of the second type of message) will be set to the sync input The second, third, and fourth flip-flops 4, 5, 6 constantly from the output of the forwarder 10 pulses receive the enabling signal (see Table 2, start of reception), In table. The 2 states of the flip-flops 4-6 before the arrival of the control signals from the outputs of the decoder 19 are indicated by

0 1-1 cycle, and after - through the first cycle.

The selection of the label from the composition of the received data is as follows.

At any time on

5, the input of the device changes the type of received message (changing the length of characters), i.e. After the silent mode, a transmitted message arrives at the device input (as indicated, only a second type message can not be received at this time). For an example in the table. 2 considers the case of receiving the first type of message. Knowing the type of previously received message (a single signal from the output of the third trigger 5 is fed to the eighth input of the decoder 19, the sixth input of which receives a single signal from the output of the pulse counter 11), the type of received communication is identified according to the data in Table. 1, and setting a single signal from the third output of the decoder 19 to the single state of the second trigger 4 (see Table 2, moment selection

5 receiving message). At the same time, the signal from the first output of the decoder 19 is set to the zero state of the fifth flip-flop 7 and the reset of the pulse counter 11 pulses (end of silence mode).

After that, the device proceeds to receive the next message, Pulse Counter 11 counts the received characters of the message in shift register 1. At the moment of reception of each character, a signal is generated for installation in a single state of a trigger that fixes the type of message received (in this case, the fourth trigger-6), which ensures verification of the correctness of the SI generation, because using the decoder 19 analyzes the incoming control signals When the first character of the next message is received, a signal is generated at the output of the pulse counter 11 to check for the presence of a CA signal. If a label is selected at a given time, a consumer receives a CA signal, using which it reads the received message in a parallel format. After the pulse counter 11 is set to zero, a new data reception cycle begins.

It should be noted that as a result of the pulse counter 11 being zeroed out after receiving the first character of the message (label), the counting is shifted by one character, i.e. the signal at its output appears at the moment of receiving the first character of the next message, and the state of the counter corresponds to the reception of the nth character. Due to the fact that information reading from shift register 1 occurs in a parallel format by a CA signal, which is generated when the first character of the next message is received, the register consists of n + 1 bits, and reading only occurs from n bits.

An error signal is generated when a message is received in cases where a violation of the correctness of the selection of the SI offset is found, which are listed in Table. 1. In this case, an error signal is issued to the consumer, and the device is switched to the phasing mode and the device operates in a manner similar to the initial switch-on. In tab. 2, cases are considered when, at the moment of receiving messages of the second and first types, the moments of the SI displacement are marked by the value of + Logs O At, which contradicts the correctness of the formation of these signals.

Claims (1)

Invention Formula A device for receiving information from a fiber-optic communication line, containing a differentiating unit, the first trigger connected in series, the pulse shaper and the unit delays, pulse counter, shift register, second delay unit, first - third elements And, second - fourth triggers, with input of differentiating unit combined with the information input of the shift register and is the information input of the device, the output of the differentiating unit is connected to the zero input of the first trigger, the direct output of which 0 is connected to the clock input of the shift register, and the inverse output through the second delay unit is connected to the single input of the first trigger, the outputs of the shift register are information outputs of the device, 5 the counting input of the pulse counter is combined with the first inputs of the first - third And elements and connected to the output of the pulse former, the second inputs of the first - third And elements are connected 0, respectively, with the first - third outputs of the first delay block, the outputs of the second - fourth flip-flops are respectively the first - third control outputs of the device, which is different because, in order to reduce the phasing time, a decoder is entered, the fourth - the sixth elements And, the OR element, the fifth trigger, whose single input is connected to the element output. 0 OR, the zero input is combined with the first input of the fourth AND element, with the first setter input of the pulse sweeper and connected to the first output of the decoder, the forward trigger output is connected to the second setting input of the pulse counter counter, and the inverse output to the second the input of the fourth AND element, the output of which is the output of the frame alignment signal of the device, the second output The 0 decoder is connected to the first input of the OR element and is the fourth control output of the device, the second input of the OR element is the control input. The device is initially set up, the single inputs of the second to fourth flip-flops are connected to the third to fifth decoder outputs, the fifth and sixth elements And are combined with the synchronous inputs of the second - fourth triggers and connected to the output of the pulse former; the second inputs of the fifth and sixth elements And are connected respectively to the fifth and sixth the outputs of the first delay unit, the outputs of the first, second, third, Five fifth and sixth elements And are connected respectively to the first - fifth inputs of the decoder, the sixth input of which is connected to the output of the pulse counter, the seventh to ninth inputs are connected to the outputs of the second to fourth triggers, respectively. 1753605 10 Table 1 table 2