SU1144099A1 - Microprogram device for data input/output - Google Patents

Abstract

1. MICROPROGRAMMING DEVICE FOR INFORMATION INPUT AND OUTPUT, containing the first memory block, interface block, synchronization block, computer counter, address counter, address register, first switch, first multiplexer, command counter and address counter outputs, respectively, are connected to the first and second the information inputs of the first switch, the outputs of which are connected to the address inputs of the first memory block, the information inputs of the first group of the first multiplexer are the information inputs of the first group of device, The first input of the synchronization block is the start input of the device, the inputs-outputs of the first group of the interface block are the outputs of the first group of the device, characterized in that, in order to increase the speed of the device and expand its application area by providing firmware information I / O control it contains the second memory block, the firmware control block, the second switch block, the information inputs of the third group of the first commutator are rj ,, j ... tator are information GOVERNMENTAL vho-. The second group of devices and the outputs of the first switch are connected to the address inputs of the second memory block, the outputs of the block of counters are connected to the information inputs of the second group of the first multiplexer, the information inputs of the address and command counters, the block of counters and the first group of inputs of the second switch the device groups, the outputs of the second memory block are the information outputs of the device, the inputs-outputs of the first memory block and the inputs-outputs of the second group of the interface block are inputs-outputs (L of the second group of the device, outputs of the first group of the microprogram control unit of coy; aineny with the corresponding control inputs of the interface block, the first and second memory blocks, the first and second switches, command and address counters, the counter block and the synchronization block , the first output of which is connected to the control register input; about the address, the outputs of which are connected to the information inputs of the firmware control unit, the outputs of the second group of which and the output of the first. the multiplexer is connected to the information inputs of the second group of the second switch, the outputs of which are connected to the information & t inputs of the address register, the second and third outputs of the synchronization unit are connected respectively to the first and second control inputs of the microprogrammed control unit, the outputs of the third

Description

the groups of which are connected to informational BXOAaNm of the third group of the first multiplexer, the control input of which is connected to the output of the microprogram control unit, the outputs of the fourth group of which are the control outputs of the device,

2, The apparatus of claim 1, wherein the firmware control unit comprises a third memory block, a buffer register, the AND element, the first, second and third groups of AND elements, the inputs of the third memory block are the information inputs of the block, the outputs of the first groups of the memory block are the outputs of the second group of the block, the output of the memory block is the output of the block, the outputs of the second group of the memory block are the outputs of the third group of the block, the outputs of the third group of the memory block are connected to the information inputs of the buffer register, the outputs of the first The first groups of which are connected to the first inputs of the AND elements of the first group, the B111 inputs of the second group of the buffer register are connected to the first inputs of the AND elements of the second group, the second inputs of the AND elements of the first and second groups and the control flow of the buffer register are the second control input of the block, the outputs the third group of the buffer register is connected to the first inputs of the AND elements of the third group, the first output buffer44099,.

The first register is connected to the first input of the AND element, the second input of which and the second inputs of the AND elements of the third group are the first control input of the block, the outputs of the AND elements of the first, second and third groups, the AND element, the fourth and fifth groups of the buffer register and the second, the third, fourth, fifth, sixth and seventh outputs of the buffer register are the outputs of the first group of the block, the outputs of the sixth group of the buffer register are the outputs of the fourth group of the block.

3. The device according to claim 1, characterized in that the gateway contains a second multiplexer, a group of registers, a block of bus drivers and a group of blocks of bus drivers, whose platoon-outputs are the inputs-outputs of the first group of the block and are connected to the information inputs of the second multiplexer The outputs of which are connected to the information inputs of the bus driver unit, the inputs-outputs of which are the inputs-outputs of the second group of the block and are connected to the information inputs of the registers of the group, all of which are connected to data inputs blokovshinnyh formers, which control inputs and control inputs of the block group of registers schinnyh formers, the second multiplexer are input by the control unit.

The invention relates to computing, and can be used in data processing systems as a subprocessor to exchange information between the I / O channel and 5 external (peripheral) devices.

The purpose of the invention is to increase the speed of the device and expand the scope of application by providing firmware control information input and output.

FIG. 1 shows a functional diagram of the device; FIG. 2 is a firmware control block; in fig. 3 - block counters; 4 shows a synchronization unit; in fig. 5 — interface block; in fig. 6 - the first switch; in fig. 7 - priority block.

The firmware for input-output information (Fig. 1) contains the first memory block 1, the second memory block 2, the firmware control unit 3, the counter unit 4, the synchronization unit 5, the interface unit 6, the command counter 7, the address counter 8 , address register 9, first switch 10, second switch 11, first multiplexer 12, information inputs 13 of the first group, input 14 Start, inputs-outputs 15 of the first group, control outputs 16 outputs 17 of the second group of microprogram control unit 3, output 18 of the block 3 firmware control outputs 19 the third group of the firmware control unit 3, the outputs 20 of the first group of the firmware control unit 3, the control inputs 21-23 of the interface 6, the control input 24 of the first memory block 1, the control inputs 25 and 26, the next in memory 2, the control inputs 27 and 28 of the first switch, the control inputs 29 and 30 of the command counter 7, the control inputs 31 and 32 of the address counter 8, the control input i of the second switch 11, the control. - -tm 34 meter blocks, the second. input 35 of syncrosis unit 5, first output 36 of unit 5

onization, the second output 37 of the onization unit, the third output 38 of the block Ñ s. synchronization, information inputs 39 of the second group, outputs 40 on the counter of 7 commands, outputs 41 on the address counter.

Block 3 of the microprogram | frame control (FIG. 2) contains the third memory block 42, the buffer register 43, the AND 44 element, the AND 45 elements of the first group, the AND 46 elements of the second group, the And 47 elements of the third group.

Block 4 counters (Fig. 3) contains a group of counters 48. Block 5 synchronization (Fig. 4) contains a trigger 4Q generator 50 pulses, the element And 51

The interface unit 6 (FIG. 5) contains the registers 52 of the group, the second multiplexer 53, the block 54 of tire formers, blocks 55 of the group of tire formers.

The first switch 10 (Fig. 6) contains the block 56 priority, the encoder 57, the block 58 of the elements ZI-OR, the decoder 59.

The priority block 56 (FIG. 7) contains AND 60 elements and OR elements 61..

The second memory block 2 (ROM) is intended for storing instruction codes and constants.

The first memory block 1 (RAM) is used for the operative storage of information for the exchange between exchange sources (I / O channel) and subscribers Sch.

Firmware control unit 3 is used to perform device control functions in accordance with the firmware stored in memory unit 42 (FIG. 2). The buffer register 43 is designed to store the codes of the operating parts of the next micro-instructions, which are read from the microprogram memory block 42. The entry of the micro-operation code into the register 43 is effected by the falling edge of the pulse tg, which is fed to the input 38 of the block 3. The set of micro-ops, issued by x by the block 3, can be divided into two parts: external and internal micro-operations. The signals of external microoperations arrive at the output 16 of the device and control the execution of operations in external with respect to the proposed device (operating devices, etc.). The signals of the internal micro-operations from the code 20 of the microprogram control unit 3 are sent to the main nodes of the microprogramming device for input-output information and control their operation.

From the outputs 33 and 35 of the register 43, micro-operations of the command end and end of operation are output, which are fed to the corresponding control inputs of the switch 11 and the synchronization unit 5, respectively.

The signals at outputs 27 and 28 and register 43 control the operation of switch 10. At exits 24 - 26, signals are generated that control the operation of inputs 2 and 1. At transceivers 24 and 25, potential signals are issued to access blocks 2 and 1, and at output 26 a pulse signal of recording information in block 1 according to a clock pulse 2g from input 37.

The outputs 21–23 of the unit 3 generate control signals of the interface unit 6.

From the codes 29 (31) and 30 (32) of the control block 3, the signals are fed to the synchronization input and the counting input, respectively, of the command counter 7 (the counter of the 8 address) and controls its operation.

The entry of information into the counters 7 and 8 and their counting is synchronized with the clock pulses supplied to the input 38 of the microprogram control unit 3. The control of the counters of block 4 is carried out in a similar way. The control signals are generated at the outputs 34 of block 3, gated with clock pulses S from the input 38 of block 3 and are fed to the corresponding inputs of the block 4 of counters. Block 4 of meters is designed to store the lengths of arrays of information exchanged between the input and output channel and external devices (through the information inputs of block 4, inputs outputs of block 1, block 6 of conjugation) The number of counters B is determined by the number of external devices — subscriber and depth of loop investments in program p, n + p. The overflow signals of the counters 48 are received by the absent unit 4 and then to the multiplexer 12, the synchronization unit 5 serves to form a clock grid of the device, which consists of three sequences of pulses D -2 shifted from one another and outputted from the generator 50 pulses (FIG. 4 a) to exits 3638 respectively. The trigger trigger 49 is designed to control the pulse generator 50. The trigger 49 is set to a single state by the trigger signal supplied to the device input 14. Resetting; Trigger 49 and blocking generator 50 is carried out on a signal. . At the end of the micro-operation, it is sent to the second input 35 of the block 5. When this potential signal appears, the clock pulse C passes through the open element I 51 to the zero input of the trigger 49 and sets it to the zero state. Interface unit 6 is used for intermediate storage of information from (on) external devices for exchange. Registers 52 (Fig. 5) are intended for storing information on the corresponding channel. The multiplexer 53 serves to control the selection of one of the buses 15 for receiving information and transmitting it to external devices. Multiplex 53 implements a system of logical functions 06-, с, (; r ... (Q, V-tlm Pt fv -tfmpl ... i 1,2,.,., R, 9 where ft is the i-ro value code bit in channel 5 coming from input-output 17-, -1,2, ..., n; d is the code size. Blocks 54 and 55 of the bus drivers are designed to control the reception and the information to the inputs- the outputs of block 6. The control of entering information into the register 52 and the exchange of data through the inputs-outputs of block 6 is carried out by micro-operations signals arriving at the inputs 2123 of block 6. Command counter 7 is used to generate and store the command address d and constants stored in block 2. The counter 8 of the address is used to generate and store the address of the numbers (data) stored in block 1. The first switch 10 (Fig. 6) is designed to switch the address when accessing blocks 1 and 2. Block 56 the priority and the encoder 57 serve to form the address when the interrupt request signals are received at the information input 39. The interrupt processing (the formation of the corresponding addresses) is performed in accordance with their priorities (Fig. 7). The interrupt signal with the highest priority from one of the outputs of block 56 is fed to the input of the encoder -, ",, 57, which forms the fixed address of the interrupt processing command. Block 58 of the ZI-OR elements switches the address in accordance with the control signals from the outputs of the decoder 59. When a signal appears at the first output of the decoder 59, the output of the switch 10 and the input of block 1 receive the address of the next command from output 40. When signals appear the second and third outputs of the decoder 59 to the output of the switch 10 and then to the address inputs of blocks 2 and 1 passes the code from output 41 or output of the encoder 57, respectively. The second switch 11 is designed to switch the code of the current address coming from the outputs 17 of block 3 and the output of multiplexer 12, respectively, and the code of the start address coming from the information inputs, depending on the signal of the microoperation. The end of the command at input 33. 7 The multiplexer 12 selects one of values of logical conditions, incoming (from the input 13 of the device exchange requirements and the output of the 4-meter block, in accordance with the control code supplied from the output 19 of the microprogram control block 3, and the identification of the address bit coming from the input 21 of block 3, Multiplexer 12 realizes the logical function), b2..lp, tx, b ,,,., hl, m2l, bi6, b., b. , b2b, ...., .- t xDDg-t, where a is the value of the modified address bit from the output 18 of block 3 of the microprogram control x-xh. laziness; B., B, ..., b are the bits of the code of logical conditions coming from the output 19 of block 3; B; b {b ;, m jlog dTCd is the number of logical conditions to be verified, where S and E are the number of logical conditions received from input 13 of the device and output of block 4, respectively). Thus, if a linear microinstruction is performed, i.e. . .,., then (a and at the output of the multiplexer 12 passes the address number of a row without change. If, bn b ..., i.e., a branch microcommand is performed in which the value of the logical condition is checked, then the output of multiplexer 12 passes the value of this condition, etc. The proposed device operates in four main modes: receiving information from the I / O channel (exchange sources); transferring information from the operational memory to subscribers; receiving information from subscribers when information is received from RAM (I / O channel memory. I, receive mode information from the I / O channel. 998 In the initial state, all memory patrons (triggers) are reset to zero, except for two triggers corresponding to the command end inputs, address 24 of block 1 of register 43 of microprogram control unit 3. The specified triggers are in one state As a result, at the input 33 of the switch 11 and the input 24 of block 1 there are single signals that allow the operation code (starting address) of the first command from the output of block 1 to pass through the switch 11 to the information input of the register 9. First NDA is stored in block 1 at address zero. According to the Start signal, which is fed to the input 14 of the synchronization unit 5, the issuing of clock pulses from the outputs 36-38 begins. On the first clock pulse from the output 36 of the synchronization unit 5, the initial address of the microprogram corresponding to the first command is entered into register 9. In the first phase of this mode, the settings of block 4 are adjusted according to the size of the zone allocated to each subscriber in block 1. The first and subsequent commands read from block 2 are interpreted in block 3 microcommands, from which ROM 2 to block 48 4 successively enter the constants corresponding to the sizes of the zones. For example, according to the first micro-command read from register 43, the unit content of the counter 7 of the commands tno is increased by an impulse 2 a micro-operation is formed at the input 30 of the corresponding element And 46 of the second group, which is fed to the input of the counter 7). According to the second microcommand containing microoperations for accessing the block, 2, corresponding microoperations at inputs 27 and 28 of register 43, ensuring the passage of the address code of the counter 7 commands to the output of the switch 10, as well as the microoperation of entering the length code into the first counter 48 of block 4 formed by the corresponding element And 45 of the first group, in the counter 48, the constant corresponding to the size of the zone allocated to the first subscriber is entered. This constant is stored in the command ROM 1 in a 9G1 cell with a single (regular) address and is in addition to the zone length code. The next microcommand increases the contents of command counter 7, and then the microoperations for block 2 and the end of the command that are in register 9 The start address of the firmware is entered, and the constant is entered in the next counter of block 4. The execution of this and subsequent firmware is carried out similarly to the described algorithm. After the constants are entered, the first phase of operation in this mode ends and the device enters the second phase — the interrogation phase of the exchange sources. In this phase, the interrogation source interrogation programs are sequentially implemented. The interrogation of sources is carried out using the multiplexer 12,. In the first microcommand in the field of logical conditions the code corresponding to the first exchange source is set, the signal from which comes through one of the inputs 13. According to the code of the logical conditions, the signal is selected from the output 19 of the microprogram control unit 3. the corresponding input 13 and, if it is equal to one, the modification of the lower address bit is made. According to the micro-command executive address that has been formed in such a way, through switch 11, it enters into address register 9, the next microcommand is read from microprogram control unit 3, and then the device operates in the service cycle of this exchange source. Another signal at the corresponding input 13 is zero, then the address modification the discharge is not produced, and at the address received from the outputs 17 and t8 of the microprogram control unit 3, the next microinstruction is read, on which the trace is sampled from block 2 guide the team. This command, similar to the one described, is carried out a firmware survey of the second source. For this purpose, in the field of logical conditions of the corresponding microcommand, the verification code of the second source is written. Then the alternative situation is again resolved and, depending on the signal from the source of exchange, there is a transition to polling the next source or servicing it. All sources of exchange can be divided into two types. Interrogation and servicing of S sources of the first type is carried out by directly checking the presence of signals at the first 5th input 13 of the multiplexer 12. Interrogation B of sources of the second type is carried out using the generalized signal of the exchange requirement received at (J, 1) -th input of inputs 13 .Fixed starting addresses that in-. The formations from the exchange sources of the second type are formed by the priority block 26 and the encoder 57. Consider the service algorithm of the exchange sources of the first type. The transition to this algorithm and the exit from it can be carried out, for example, by an unconditional branch command, the address of which is specified in the code of the command for polling the exchange source. If there is no exchange request from the next source, then the contents of command counter 7 will be increased by firmware, if such a requirement exists, then counter 7 from block 2. through the information inputs, the unconditional branch address is entered, from which the first servicing command of the given source is then read from block 2. I In this command, besides the operation code, the address of the initial cell of block 1 is set, to which information from the first exchange source will be entered. Then, a micro-operation signal arriving at one of the outputs 16 of the external micro-operations of the microprogram control unit 3 causes the first information word to be transmitted from the exchange source. Further, according to the signals of the corresponding microoperations, arriving at the inputs 26 of block 1 and 34 (e1,2, ... ..ij j) of block 4 of the counters, the information is entered in block 1 and the content of the corresponding counter 48 of block 4 is enlarged. The counter of the address 8 is held and a check is made for the presence of the overflow signal of the counter 48. If there is no overflow signal,

The microprocessor control unit 3 again enters the micro-operation of recording information in block 1 and increasing the contents of the corresponding counter 48 (at the output of the corresponding element 45).

Thus, the operation of the device continues until

1 it will not be recorded completely in all information from this exchange source. After the last information word is recorded in block 1, the corresponding counter overflows.

48 of block 4, a single signal appears at the corresponding bit at the output of block 4. According to the code of the logic condition coming from the output 19 of microprogram control 1, this signal modifies the fallen address bit, and the next is a micro-command that is used to access block 2 for the next command, as well as an increase in the contents of the counter 7, and for the microoperation End of the command, arriving at the input 33 of the switch 11, there is a transition to the implementation of the firmware of the next command. With this from the block

2, the unconditional command to poll the next exchange source of the first type is read.

Thus, the polling firmware is implemented in accordance with

described by the algorithm. I

The service (reception of information) from the exchange sources of the second type is characterized in that the initial addresses of the zones of RAM 2, in which information is entered from these sources, are formed by the encoder 57, respectively. with signals from priority block 56 (Fig. 6- 7). Priority unit 56 selects the exchange source, from which the exchange request signal is received and which has the highest priority, and generates a signal at one of its outputs. According to this signal, the encoder 57 generates a fixed address, which, in accordance with the control signals at inputs 27 and 28, which excite the corresponding output of the decoder 59, passes through block 58 of the ZI-SH1I elements to the output of switch 10 and in block 1 this information is recorded in this fixed address . Thus, the exchange is carried out on the type of mailboxes, through

orders can be issued to subscribers in the same way as the described mode, the difference being that only one word (order) is issued, and at the output 16 of the device, a micro-operation is generated identifying this exchange.

Thus, by the end of the operation of the device in the first mode, information from S + Sg sources was recorded in the corresponding zones of unit 1.

The mode of information transfer to the subscriber.

After the last command of the subroutine 1 receiving information from the exchange sources is executed, the information is restored in the counters 48 of block 4 in the same way as the first mode.

Then, in accordance with the commands read from block 2, microprogram control unit 3 implements the microprograms for issuing information to subscribers from block 1 through the interface block and the input-outputs 15. Microprogram control unit 3 signals the beginning of an information cycle by forming a micro operation on one of the exits 16

When working with the next subscriber from block 1, information words are sequentially read, which. are entered into one of the registers 52, and then through the block 55, the bus drivers are passed to the input-output 15.

Information is sampled from block 1, the content of the corresponding counter 48 of block 4 is increased, information is entered into register 52 and sent to inputs / outputs 15 by micro-ops signals generated by microprogram control unit 3. These microoperations occur at the output 25, respectively, of the registrar 43, at the output of one of the even elements And 45, at the output of one of the elements And 47 and at the corresponding output 23 of the register 43..

In parallel with the information, the subscriber in the cycle performs a verification of the presence of an overflow signal from the corresponding counter 48 of block 4. When an overflow signal appears on one of the outputs of block 4, the address bit is modified and the last microcommand is performed. block H

13

and following the instruction of the team (commands to send information to the subscriber).

The operation of the device in this mode ends after the command is read and executed by sending information to the last subscriber.

The mode of receiving information from subscribers.

In this mode, information is received from subscribers coming to the inputs-outputs 15, and recorded in block 1. When receiving information and from the i-ro subscriber, microprogram control unit 3 generates at the inputs 21 a code of control signals, by which receipt is allowed information from the corresponding input-output 15 through the multiplexer 53, the block 54 bus drivers to the inputs-outputs of the second group of block 6 and further through the I / O to block 1 ..

Information from subscribers is entered into zones of a fixed-length block 1 in a manner similar to the first mode.

PeaftiM inject information into the I / O channel.

The output of the information recorded in block 1 is carried out according to the corresponding microprograms implemented by block 3 of the microprogram of the control. At that, the firmware control unit 3 on the outputs 16 and 20 forms external microoperations, which signal the information to the channel, and the internal microoperations of accessing block 1, increasing the content of the corresponding counters 48 of block 4 (and checking for overflow signals) and counter 8, control switch 10, access to block 2 when reading the next command

The end of the operation of the device (the completion of the exchange macrocycle: exchange sources - block 1, block 1 - subscribers, subscribers - block 1, block 1 channel) occurs after execution

4409914

The last command to issue information from block 1 to the channel. In the last microcommand of the corresponding firmware, at input 35 of register 43 of block 3, a signal is generated which, after 23, enters input 35 of synchronization block 5 and zeroes trigger 49. The next exchange macro cycle starts after submission

10 on input 14 of the Start command.

The availability of software and hardware and software in the proposed device allows the flexibility to change the algorithms for executing the macro 15 exchange cycle. So, for example, in the device according to the program recorded in block 2, information is exchanged between sources and subscribers in the sequence: i-th source 20 block 1, block 1 - i-th subscriber, i-th subscriber - block 1, block 1 - channel, according to the requirements of the exchange. In this case, the total time required is reduced by eliminating the phases.

25 enter the constants in those counters of block 4 that correspond to sources that do not generate exchange request signals.

JQ The choice of one or another exchange algorithm is made taking into account the nature of exchange sources and subscribers, and their change is made by making adjustments to the programs recorded in block 2 at the production stage.

The proposed device significantly exceeds the known for speed when working with subscribers, characterized by different information arrays.

In addition, the proposed device has a wider range of applications due to the presence of special hardware-firmware

means, allowing Kitsykhs to bidirectionally exchange information and flexibly change the exchange algorithm.

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Claims (3)

1. MICROWARE DEVICE FOR INFORMATION I / O, containing the first memory block, a pairing block, a synchronization block, a command counter, an address counter, an address register, a first switch, a first multiplexer, the outputs of a command counter and an address counter are connected respectively to the first and second information the inputs of the first switch, the outputs of which are connected to the inputs of the address of the first memory block, the information inputs of the first group of the first multiplexer are the information inputs of the first group of the device, the first input d synchronization block is the input of the start of the device, the inputs and outputs of the first group of the pairing unit are the outputs of the first group of the device, characterized in that, in order to improve the performance of the device and expand its scope by providing microprogram control of the input-output of information, the second block is introduced into it memory, microprogram control unit, counter unit second switch, information inputs of the third group of the first switch are information inputs of the second group devices, and the outputs of the first switch are connected to the address inputs of the second memory block, the outputs of the counter block are connected to the information inputs of the second group of the first multiplexer, the information inputs of the address and command counters, the counter block and the first group of inputs of the second switch are information inputs of the third device group, the outputs the second memory block are the information outputs of the device, the inputs and outputs of the first memory block and the inputs and outputs of the second group of the interface block are inputs and outputs in Ora device group, the outputs of the first group microprogram control unit connected to the respective control inputs of the interface unit, the first and second memory blocks, the first and second switches, counters command and address counter unit and the sync block, a first output of which is connected to the control input of the ^register; addresses · whose outputs are connected to the information inputs of the microprogram control unit, the outputs of the second group ^{1 of} which and the output of the first multiplexer are connected to the information inputs of the second group of the second switch, the outputs of which are connected to the information inputs of the address register, the second and third outputs of the synchronization unit are connected, respectively with the first and second control inputs of the microprogram control unit, the outputs of the third group of which are connected to the information inputs of the third group of the first o multiplexer, the control input of which is connected to the output of the microprogram control unit, the outputs of the fourth group of which are the control outputs of the device. 2. The device according to π. 1, characterized in that the microprogram control unit contains a third memory block, a buffer register, an AND element, a first, a second and a third group of AND elements, the inputs of the third memory block are the information inputs of the block, the outputs of the first group of the memory block are the outputs of the second block group, the output of the memory block is the output of the block, the outputs of the second group of the memory block are the outputs of the third group of the block, the outputs of the third group of the memory block are connected to the information inputs of the buffer register, the outputs of the first group of which are are dined with the first inputs of AND elements of the first group, the outputs of the second group of the buffer register are connected to the first inputs of AND elements of the second group, the second inputs of the elements of the first and second groups and the control input of the buffer register are the second control input of the block, the outputs of the third group of the buffer register are connected to the first inputs of the AND elements of the third group, the first output of the buffer register is connected to the first input of the And element, the second input of which and the second inputs of the And elements of the third group are the first control input of the block OK, the outputs of the And elements of the first, second and third groups, the And element, the fourth, fifth groups of the buffer register and the second, third, fourth, fifth, sixth and seventh outputs of the buffer register are the outputs of the first block group, the outputs of the sixth group of the buffer register are the outputs of the fourth block groups. 3. The device according to p. 1, characterized in that the interface unit contains a second multiplexer, a group of registers, a bus driver unit and a group of bus driver units, the IO outputs of which are the inputs and outputs of the first group of the unit and connected to the information inputs of the second multiplexer, outputs which are connected to the information inputs of the block of bus shapers, the inputs and outputs of which are inputs and outputs [of the second group of the block and are connected to the information inputs of the registers of the group, the outputs of which are connected to and formational input block bus drivers, which are control inputs and control inputs of the register group block bus drivers, the second multiplexer are control inputs bloka.-