SU940151A1 - Information exchange device - Google Patents

Description

(5) DEVICE EXCHANGE INFORMATION

The information exchange device relates to digital computing and serves to organize the process of information exchange between the I / O channel and external devices.

Information exchange devices are known, including priority selection units, communication registers, gateways, tl and t2 logic circuits. to

However, these devices do not ensure the independence of the priority of interface blocks from their physical location.

The closest to the proposed 15 in technical essence and the achieved result is an information exchange device comprising an input / output channel, a group of interface blocks with external devices, and a multichannel trigger generation unit Z.

I A disadvantage of the known device is that it has a low speed due to the sequential order of maintenance of exchange requirements and lack of flexibility due to the lack of the possibility of promptly changing the priority of external devices.

The purpose of the invention is to increase speed and flexibility.

Claims (3)

This goal is achieved by the fact that in an information exchange device containing an input / output channel, a group of interface blocks with external devices and a multichannel trigger generation unit, each channel of which contains the first AND element, with the outputs of the control signals of interface blocks with external devices connected to the input of the control signals of the I / O channel, the inputs of the control signals of the interface blocks with external devices are connected to the output of the control signals of the I / O channel, the first information The input and output channels of the input-output channel are connected to informational, respectively, outputs and inputs of the interface box with external devices, the output of the interface unit request with an external device is connected to the first input of the first element AND of the corresponding channel of the trigger signal block, the output of the first the element And channel of the block forming the start signals are connected to the trigger input of the corresponding block with the external device, the second information input and output of the I / O channel are connected to and corresponding to the input and output of the device, the code input of the interface unit with the external device is connected to the corresponding input of the group of code inputs of the device, the output output of the interface unit with the external device is connected to the corresponding output of the group of output devices of the device; and a trigger, the second and third elements AND and an element NOT are inputted to each channel of the formation of the trigger signals; moreover, the trigger output of the channel of the formation of the trigger signals is connected to the first input V the first element of the channel of the formation of the trigger signals is connected to the output of the I / O channel sample signal the output of the second element of the channel of the formation of the trigger signal is connected to the second input of the first and the first input of the third element And the channel of the block of formation of the start signals, the output of the requirement of the block of interface with the external device is connected through the element NOT of the corresponding channel of the block of the formation of the trigger signals with the second input the third element AND the corresponding channel of the trigger generation block; the outputs of the third elements AND channels of the trigger generation block are connected to the request inputs of the variable priority block, each output of which is connected to the trigger input of the corresponding channel of the trigger shaping block, and the output is connected to the trigger input of the variable priority block. The variable priority block contains a group of priority registers, a group of comparison circuits, an estimator, and an OR element; the input of the counter is connected to the output of the OR element; the output of the counter is connected to the first inputs of the comparison circuits, whose outputs are connected to the corresponding outputs of the block; the outputs of the priority registers are connected to the second inputs of the respective comparison circuits, and the trigger input and the query inputs of the block are connected to the inputs of the OR element. FIG. 1 shows a block diagram of the device; in fig. 2 shows an embodiment of the block diagram of the interface unit with external devices. The communication device of FIG. 1 contains an input / output channel 1, a variable priority block 2, a multichannel trigger generation signal block 3, interface blocks with external devices, priority registers 5, comparison circuits 6, counter 7, OR element 8, E triggers, And 10 elements, NOT elements 11, third AND 12 elements, first AND elements 13, triggering input AND, output 15 of control signals, input 16 of control signals, information input 17, information output 18, code input 19, code output 20, output 21 of demand, the first 22 and second 23 information inputs of the input-you channel odaJpervy 24 and second 25 data outputs, the entrance 26 and exit 27 control signals 28 output samples. The interface unit with external devices (Fig. 2) contains a communication node 29 with a channel, a buffer lumen node 30, a command decoder 31, an address decoder 32, a communication device with an external device, a node 3 for receiving and generating requests. The I / O channel, which can be performed as in a known device, is intended for organizing the exchange of information between external devices via interfacing blocks k and the main memory of a computer via processor commands. Block 2 is used to establish and prioritize the block A of the conjugation. Unit 3 controls the transmission of the Sampling signal from the channel and the Sampling from block 2, depending on the signal. The requirement for the interchange from the interface blocks. The block k of the reference is intended for the connection of the external 59 devices with the I / O channel, which are different in terms of the speed of operation and the information transmitted by the external 59. The priority register 5 is used to set the priority code to the corresponding conjunction block C. The number of these nodes and the number of registers 5 at each node are equal to the number of matching blocks. Comparison schemes 6 are designed to compare the priority code set on registers S, and the code from counter 7- Counter 7 sequentially recalculates the priority numbers, starting with the first and ending with a number equal to the number of 4 match blocks. The OR 8 element sends recalculation signals to counter 7, the OR element 8 receives the Sample signal from the channel first, and then the Sample signal from block 3, if the interface unit with the current priority does not have the Exchange Requirement signal. Triggers 9 are used for storing the Sample signals coming from block 2. Element I 10 is designed to generate a control signal by matching the Sample from the channel and the Sample signals. Elements And 12 and 13 pass the control signal from the element 10 to the interface blocks or block 2, depending on the presence or absence of a signal. The exchange requirement from the interface block C. The HE element 11 serves to invert the. Demand exchange signal. The communication unit 29 with the channel is designed to perform all communication procedures with the channel. The buffer memory node serves to collect temporary storage and perform logical operations on the information being transmitted. The decoder 31 commands accepts commands and control words from the channel, interprets them and generates control actions. The address decoder 32 serves to determine and allocate addresses of the block t with voltage and external devices and generate the appropriate control signals. Node 33 is designed to perform all communication procedures with external devices. The node 3 receiving and generating requests serves to generate a signal. Requesting the exchange and reception of a signal. A sample, after receiving a signal. The device works as follows. 16 Before starting work, all registers 5 are set to a certain position corresponding to the priority code for each of the interface blocks. At the same time, there should not be identical codes in different registers 5, since in this case the same priority will be assigned simultaneously to two blocks of the C interface. The sampling signal from the channel is fed to the input of the counter 7 through the element OR 8 and the leading edge sets the first discharge of the counter 7 to the single position. Counter code 7 is compared in comparison circuits 6 simultaneously with codes of all registers 5. Comparison circuit 6, on which the comparison took place, generates a signal that sets the corresponding trigger 9 in the one state. On the trigger one, and if the sample signal is present from the channel, the corresponding element And 10. The signal from the output of the element And 10 enters the input of the elements And 12 and 13, if in block 4 there is a signal Requirement of exchange, then the element And 13 triggers and the signal Sampling from the output of the element And 13 enters the block t, Otherwise the AND gate 12 is activated and the unused sample signal from the output of AND gate 12 sets a null state corresponding trigger 9 and via OR gate 8 is added to the counter unit 7 starts the analysis of the next priority number. The new state of the counter 7 is compared in the comparison circuit 6 with the codes of all the registers 5. The comparison now takes place in the next comparison circuit 6, it generates a signal which sets the corresponding trigger 9 in one position, etc. The introduction of additional elements and a variable priority unit distinguishes the invention from the known device in that it increases its speed and flexibility due to the availability of a quick change of priorities to the interlock units without changing their physical location, without the need for long and complex commutations and permutations; set the appropriate switches. The use of such devices is important, as changing the priority sometimes needs to be done in the process of solving one or a group of tasks, when the importance of information from external subscribers changes, and the time for rearrangement and switching of interface blocks is spent with little or, in general, such a resetting (switching / not possible. Claims of the invention: 1. An information exchange device comprising an input / output channel, groups of interfaces with external devices and a multichannel signal generating unit The start-up, each channel of which contains the first element I, and the outputs of the control signals of the interface blocks with external devices are connected to the input of the control signals of the I / O channel, the inputs of the control signals of the interfaces block with external devices are connected to the output of the control signals of the channel I / O, the new information input and output of the I / O channel are connected to the information outputs and inputs of the interface blocks with external devices, the output of the interface block with the external device the device is connected to the first input of the first element AND of the corresponding channel of the trigger generation unit, the output of the first element AND of the channel of the formation of the trigger signals is connected to the trigger input of the corresponding interface unit with an external device, the second information input and the I / O channel are connected to the information input the input and output of the device, the code input of the interface block with an external device is connected to the corresponding input of the group of code inputs of the device, the code output of the block (interface with an external device is connected to the corresponding output of the output group of the device, characterized in that, in order to increase speed and flexibility, it contains a variable priority block, and a trigger, second and third elements AND and the element is NOT, and the trigger output of the channel of the block formed by the start signals is connected to the first input of the second element AND of the channel of the formation of the trigger signal; the second inputs of the second elements AND of the channel of the signal formation the trigger input is connected to the output of the I / O channel sampling signal, the output of the second element AND channel of the trigger generation unit is connected to the second input of the first and the first input of the third element AND channel of the trigger generation unit, the output of the interface block request is connected to an external device channel of the block forming the start signals with the second input of the third element And the corresponding channel of the block forming the start signals, the outputs of the third elements And channels of the block f rkmrovani trigger signals are connected to inputs of variable priority interrogation unit, each output of which is connected to the input trigger signals of the respective channel start forming unit, and the output sample input-output channel signal is connected to the trigger input of variable priority block. 2, The device according to claim 1, wherein the variable priority block contains a group of priority registers, a group of comparison circuits, a counter and an OR element, the counter input connected to the output of the OR element, the counter output connected to the first inputs of the comparison circuits , the outputs of which are connected to the corresponding outputs of the block, the outputs of the priority registers are connected to the second inputs of the respective comparison circuits, and the trigger input and the request inputs of the block are connected to the inputs of the OR element. , Sources of information, are irrelevant in the examination during the examination 1. USSR author's certificate №, cl. G About F 3/04, 1976. 2. Authors certificate of the USSR 528561, cl. G 06 F ЗМ, 1976. 3.Kagan BM, Kanevsky M, M. Digital computers and systems. I., Energie, 197, p. 558 (prototype). I lf -.... 1J