SU1656536A1 - Device to check microprocessor control signals - Google Patents

Abstract

The invention relates to digital computing and can be used in the construction of microprocessor systems and microcomputers with control. The purpose of the invention is to increase the reliability of control of microprocessor control signals. The device contains a controlled microprocessor, a microprocessor state word register, a cycle decoder, an encoder, a counter, a persistent storage device, four triggers, ten AND elements, five OR elements, an OR NONE element, an NOT element. The essence of the invention is to increase the reliability of control. generating microprocessor control signals of the KR580IK80A type by limiting the time intervals during which the supply of control signals to the bits of the control bus is allowed 4 or less.

Description

The invention relates to digital computing and can be used in the design of microprocessor systems and microcomputers with control.

The aim of the invention is to increase the reliability of control of microprocessor control signals.

FIG. 1 shows a functional diagram of an apparatus for monitoring microprocessor control signals; in fig. 2 shows the time diagrams of the device operation during the M1 cycle when accessing the zero page of the ROM, FIG. 3 - timing charts of the device when referring to page No. 1 of the ROM; in fig. 4 a and b shows the time diagrams of the device when referring to pages No. 2 and fxb 3 ROM, respectively.

A device for monitoring microprocessor control signals contains a controlled microprocessor 1, a register 2 microprocessor state words, a decoder for cycles 3, an encoder 4, a counter 5, a permanent memory block 6, the first 7, the second 8, the third 9 and fourth 10 triggers, first 11. second 12, third 13, fourth 14, fifth 15, seventh 16, ninth 17. sixth 18, eighth 19, tenth 20 elements And, first 21, second 22, third 23, fourth 24, fifth 25 elements OR, element OR NOT 26, element NOT 27

Positions 28, 29, 30 denote the first, second, and third inputs of the device, respectively, 31, 32. 33, 34, 35, the first, second, third, fourth, and fifth outputs of the microprocessor, respectively, which form the control bus, 36 is the microprocessor data bus , 37 - output of the element NOT, 38, 39, 40. 41 - first, second, third,

about ate about ate

Oj

about

the fourth outputs of the ROM 6, respectively, 42 - the output error of the device.

The microprocessor 1 serves to process the information arriving at its inputs. In relation to the device, it is the Control object.

Register 2 of the microprocessor state word is used to receive, store and output a word — the microprocessor state.

The decoder 3 cycles is used to convert the code of the state word to the code of one of the ten cycles of the microprocessor 1.

The encoder 4 serves to convert the code of the microprocessor's cycle of operation into the code of the address of the page of the ROM 6 corresponding to this cycle.

Counter 5 is used to count the number of pulses of the clock frequency of each cycle of the microprocessor and issue this number as the address code of the word page ROM 6.

The ROM 6 is used to store and output inverse values of control signals that form words and define the limits of allowed time intervals for issuing control signals of the microprocessor in each clock cycle of each cycle.

The trigger 7 serves to organize such a strict sequence of arrival of clock pulses from inputs 28 and 29 of the device to the counting input of counter 5, when the first phase clock pulse from input 28 is fed to the counter, and then the second phase clock pulse from input 29.

The trigger 8 serves to determine the presence or absence of the Sync control signal (SYNC) in the allowed time interval. So, if there is no signal, then the trigger is in the single state, if the synchronization signal is detected, then the single synchronization signal supplied to the installation input to the O trigger 8, it is reset to the zero state. In one state, the trigger 8 is set on the trailing edge of the pulse arriving at its sync input from the output 38 of the ROM 6.

Trigger 9 is used to determine the presence or absence of a control signal Reception Information (DBIN) at the allowed time interval in all cycles except the cycle M1, in order to eliminate a false error signal at the output 40 of the device during the transition from the cycle M1 to the cycle MZ (M5 M7) and M9. Otherwise, it works similarly to trigger 8.

The trigger 10 serves to determine the presence or absence of a signal. Information Issue (WRITE) at an allowed

time interval. It works similar to trigger 8.

Element I 11 serves to prohibit the issuance of a clock signal to the counting input of the counter 5 from the device input 29 when the synchronization signal is present in the microprocessor control bus bits.

Element And 12 serves to set counter 5 to the state corresponding to

word 1 ROM 6, when moving from cycle M1 to other cycles of the microprocessor 1. (Element And 13 is used to supply a single signal to the input of the installation in O of counter 5 when switching from one cycle

(except for the cycle M1) to another cycle of the microprocessor 1.

Element And 14 is used to signal 1 to the input of the installation in O of the trigger 9 when performing a cycle M1 every time the clock pulse arrives from the input 29 of the device. This is necessary to avoid a false error signal when going from a cycle M1 to a cycle MZ (M5, M7) and M9.

Element AND 15 is used to control the absence of a synchronization signal at forbidden time intervals. At these intervals, the inverse synchronization signal, output from the output 38 of the ROM 6, is equal to 1 and unlocks the And 15 element. If

the time from the microprocessor is given the Synchronization signal to the control bus, then as an error signal it passes through the AND 15 element and the OR 24 element to the output 42 of the device error.

Element And 16 serves to control the absence of a signal Reception of information at forbidden time intervals. Works similar to element 15.

Element And 17 serves to control the absence of a signal. Issuing information at forbidden time intervals. Works similar to element 15.

Element And 18 is used to issue a signal Error on the fourth input element

OR 24 when there is no Sync signal at the allowed time interval.

Element AND 19 is used to generate an Error signal at the fifth input of the element OR

24 in the absence of a signal Reception of information on the allowed time interval.

Element AND 20 is used to output an Error signal to the sixth input of the element OR 24 in the absence of a signal. Issuing information in the allowed time interval.

The OR element 21 serves to receive clock signals arriving at its inputs and output them to the counting input of counter 5.

The element OR 22 is used for occurrence 1 at the direct output of the trigger 7, both when a sync signal appears at the input 28 of the device and when the sync signal appears at the input 29 of the device.

The OR 23 element serves to organize the resetting of the contents of counter 5 as a common signal Reset from the device input 29, and when switching from one cycle (except for cycle M1) to another cycle of operation of microprocessor 1.

The OR 24 element is used to generate a synthesis signal Error at the output 42 of the device error when the microprocessor 1 incorrectly issues the control signal bus lines into the control bus sync SYNC, Reception of information DBIN, Information output, WRITE.

The OR 25 element serves to feed a single signal to the input of the flip-flop 9 both during the M1 operating cycle and when it appears in other operation cycles at the allowed time intervals of the Acceptance of Information signal.

The OR-NE 26 element is used to send a single signal to the enable input of the counter 5 when the control bus does not have a confirmation signal for HLDA and Waiting WAIT and supplying the enable input for the counter 5 for a zero signal if at least one of the Acceptance and Waiting signals is present.

The NOT element 27 serves to obtain a non-inverted signal. Issuing WRITE information for the operation of the control circuit.

The input 28 of the device is used to supply the clock pulses of the first phase f 1.

The input 29 of the device is used to supply the clock pulses of the second phase f 2.

The device input 30 serves to signal the operator to reset at any time to stop monitoring.

The output 31 of the microprocessor 1 is the first output of the microprocessor and is used to issue a control signal Standby.

The output 32 is the second output of the microprocessor 1 and is used to issue a control signal HLDA Confirm capture.

The output 33 is the third output of the microprocessor 1 and is used to issue a control signal SYNC Sync,

Output 34 is the fourth output of microprocessor 1 and is used to issue

control signal DBIN Reception information.

The output 35 is the inverse of the fifth output of the microprocessor 1 and serves to issue a control signal WRITE Information output.

Outputs 31, 32, 33, 34, 35 of microprocessor 1 form a control bus, which is monitored.

The group of outputs 33 of microprocessor 1 is a data bus. The output 37 is the output of the element HE 27.

The outputs 38, 39, 40, 41 of the ROM 6 are used to output word codes from the ROM 6.

Device output 42 is an error output.

FIG. 2 shows time diagrams of the device operation when referring to the zero page of the ROM.

FIG. 3 shows the timing diagram of the device when accessing the first page of ROM 6.

FIG. 4.a shows the time diagrams of the device when accessing the second page of ROM 6.

FIG. 4.6 shows time diagrams of the device operation when referring to the third page of ROM 6.

The So-Sio symbols denote words stored in ROM 6 and containing the codes of inverse values of the control signals SYNC, DBIN, WRITE, as well as the direct value of the RESET signal

The device works as follows.

Before starting operation, a high level signal with a duration of at least three periods of the clock frequency of the microprocessor 1 is applied to the reset input of the device 30, by which the microprocessor is reset. Counter 5, register 2 microprocessor status words, trigger 7 are set with the same signal to the initial zero state. After that, the microprocessor starts the clock cycle T1 of the computer sampling cycle of the command M1 (see Fig. 2). Non-overlapping sequences of clock pulses of the first Ф 1 and second Ф 2 phases, respectively, arrive at the first and second inputs 28 and 29 of the device synchronization.

If the first pulse of the phase F 2 arrives, it goes to the first input of the element 11 and through the element OR 22 nl i the trigger input 7 trigger, which on the trailing edge of the pulse of the phase f 2 sets n state 1 and generates a single signal to the third input of the element i 11 But since this moment is already locked by the zero signal from the second input 29 of the device synchronization, the pulse of the phase F 2 does not arrive at the counting input of the counter 5. If the first pulse arrives at the phase F 1, it arrives at the first input of the element OR 21, from the output of the element OR 21 passes to the counting input tchika 5, and also sets the flip-flop 7 in the state 1. That allows the passage of the phase 2 pulses F in the absence of the synchronization signal input at the inverse element 11 and output from the microprocessor 33 1.

In counter 5, when a pulse appears on its counting input, it is checked whether there is a single signal on its enable input that comes when there are no WAIT Wait and HLDA Capture Confirmation signals in the bits of the microprocessor 1 control buses. outputs 31 and 32 of microprocessor 1, respectively, through an OR-NOT 26 element. In the absence of these signals, the counter begins to count the pulses on their falling edge in order to exclude the races of the Waiting signal, which is set to 1 on the leading edge of the imp the pulse of the phase F 1 and the pulse itself of the phase F 1. When at least one of the signals at the outputs 31 and 32 of the microprocessor 1 appears, the counting stops and counter 5 remembers its state in order to continue counting when these signals are removed. Each machine cycle is accompanied by The synchronization signal in the T cycle. 1. At the same time, the microprocessor state word 1 is output to the microprocessor data bus, which determines the actions that will be performed in the given machine cycle. By coincidence of the signals F 1 1 and E 1, the status word is written into 8 - bit register 2 microprocessor state words C of the output group of the register 2 and the state word enters the output group of the cycle decoder 3, which determines which of the cycles is executed in In this case, and this information is in the form of a single signal to one of ten of its outputs, which are connected to the inputs of the encoder 1 Encoder 4 converts the loop code into the code of the address of the ROM page in the corresponding loop and outputs this code for higher-order rpynnv bits The same time from CPTP 5 enters the group of lower-order bits of the address phpdch ROM 6 the number of counted pulses n the PDRD of the trouble code for this page and this page: i I Iv3v 6 Address pgilrpltppo ROM 6 p; i i / mg ml 4 straps each of which) H th and i ny em a specific group of the cycle and pages. i a cycle of Ml (see fi P Chza

page - cycles M2, M4, MB, M8, M10 (see Fig. 3, a and b), second page - cycles MZ, M5, M7 (see Fig. 4, a), third page - cycle M9 (see Fig. 4.6. Such a partition

The address space is explained by the fact that each page is associated with cycles that correspond to similar control signals during their execution.

0In the event that the encoder does not

If a page address code is received, such as in T1 cycle, the zero page is accessed, since the cycle M1 is positive for all commands, and in the T1 cycle, control signals are issued that are the same for all cycles. At the addresses received at the inputs of ROM 6, words are extracted from it that contain the inverse values of the control signals.

0 microprocessor Synchronization, Reception of information, Issue of information and in a direct form the value of the signal End of cycle.

SYNC, DBIN value. WRITE signals SYNC, DBIN, WRITE are fed to the first inputs of the And 15, 16. 17 elements, respectively, to the second inputs of which direct values of the control signals from the outputs 33, 34 of the microprocessor are received.

0 1 and output 37 of the element is NOT 27, respectively. In this case, the absence of pulses of these control signals at forbidden intervals is checked. Suppose that at a given moment in time (for example, in the tact of the TZ of cycle 5 of M1) there should not be a SYNC Synchronization signal (see Fig. 2). Then, in the corresponding moment of the ROM 6 word, SYNC - 1 must be written. This signal opens the element And 14 and in the case of

0 if the synchronization signal is false, then this signal will pass through the element AND 14 to the first input of the element OR 24, from the output 42 of which a signal will be given

mistakes. If the signal is synchronized

5 must be in this cycle (for example, in cycle T1 of the cycle M1). then from the ROM 6, the SYNC-0 signal will be read, which locks the AND 15 element for the duration of the SYNC signal. Similarly, the DBIN signals control signaling schemes work. Receiving information and WRITE Information output.

The inverse values of the signals SYNC DBIN, WRITE also come from the outputs 38 39, 40 respectively to the synchronization inputs of the triggers 8, 9, 10 and to the first inputs of the elements 18, 19, 20. The inputs to the O of the triggers 8, 9, 10 are supplied monitored values of the signals SYNC, DBIN, WRITE, respectively, directly

control at the allowed time intervals.

Consider the operation of the control circuit using the Sync signal as an example. At cycle 73 of cycle M1, a SYNC 1 signal is read from ROM, which is fed to trigger trigger 8 and to the first input of the element 18, At the end of cycle M1 in cycle 1} of any cycle, the SYNC signal should appear and the SYNT signal is read from ROM 6. In this case, the trigger 8 is set to 1 at the falling edge of the 5VNC 1 signal, and the SVKGS 0 signal is applied to the trigger synchronous input 8 and the initial input of the And 18 element for a time equal to the allowed time interval for the SYNC signal . Puo. ™ SYG ML SYNC didn’t seem to be at the allowed time interval because of an error in the operation of the calf proc: ccr 1 Then in the next (C01 .1c from the ROM 5, the signal - 1 will be read element 18 opens it, as a result of which a single signal from trigger 7 enters through element OR 24 at output 42 as an ensuing error. If W SYNC 1 is wired for the allowed time interval, then it enters the installation input at O1 , the trigger 8 is cleared to O and therefore at the next moment of time the error signal is not issued

The DBIN and WRITE signals are controlled in the same way as the SYNC signal, only the DBIN signal in the M1 cycle is not monitored, as in the M1 cycle, the first output of the cycle decoder 3 to the input of the 1/1 14 element is given a single signal that opens this element and at F2 - 1 to the input Installation in the Trigger 9 via the elements of AND 14 and OR 2G a single signal is applied. This is necessary to prevent the issuance of a false error signal during the transition from the cycle M1 to the cycle MH (M5, M7) and M9.

From output 41 of ROM 6, an impulse is also output. End of cycle R, which indicates that 1 cycle executed by the microprocessor is completed and it is necessary to proceed to the next cycle. The transition to the next cycle is as follows. All microprocessor cycles, except for the cycle M1. include three cycles (T1, T2, TZ), only the cycle M1 can have four or five cycles. Thus, if the cycle being executed was not the M1 cycle, then the counter 5, having counted three cycles, outputs to the inputs of ROM 6 an address code for which the signal R 1 is read. This signal from output 41 of ROM 6 is fed to the second inputs of elements 12 and 12 13. If the M1 cycle is not performed, then a zero signal is output from the first output of the decoder, which locks the And 12 element and unlocks

Element I 13, through which the signal N - 1 from the output of ROM 6 is fed to the second input of the element OR 23 and then to the input of the installation in O of the counter 5. which is set to the zero state, which corresponds to the word So stored in the ROM by zero address.

The moment of transition from one cycle (except cycle M1) to another is explained by the time diagrams shown in FIG. 3 and 4. Let us consider how the transition from the cycle M1 to other cycles occurs. The cycle M1 can have four or five cycles. To determine how many cycles it has

5, this cycle M1, uses the Synchronization signal, the appearance of which is analyzed after the end of the right clock cycle. With "smart 5 in this case gives the code address of the word in the zero page ROM 6,

0 from which the signal R - 1 is read. Which, as in other cycles, comes from the output 41 of the ROM b to the second inputs of the And 12 and 13 elements. But the And 13 element is closed by a single signal applied to its inverse

5 input from the first output of the decoder 3 The same signal arrives at the first input of the element And 12, and if the synchronization signal occurs in the next cycle, through the element 12 it will go to the input of the counter installation

0 to the state corresponding to the word Si stored in ROM 6.

Setting the counter to the state corresponding to the word Si, and not So, is necessary due to the fact that in this case the fifth

5 cycle T5 of the cycle M1 turned out to be the first cycle T1 of the next cycle, followed by the second cycle T2, and so on. If in the fifth cycle the SYNC signal is not detected, then despite the fact that R - 1, the counter continues counting and issuing the code addresses in the ROM b and at the falling edge of the pulse phase F2 of the clock T5 is set to R - 0. After the end of the clock T5 of the cycle M1, the counter 5 outputs the address code of the word zero page ROM 6. by which the word is read, where the bit R is 1, and again analysis of the occurrence of the synchronization signal. When it appears, the passage of the pulses of phase F2 through the element OR 24 is prohibited, counter 5 is set to the state corresponding to the word Si in register 2 of the word of the microprocessor state, a new word of the state is written and the next cycle begins.

5The prohibition of the pulses of phase F2 at the moment

Claims (2)

the passage of the synchronization signal is necessary so that the counter 5 cannot output the code of the address of the word without indicating the code of the address of the new page of ROM 6, i.e. until register 2, the microprocessor status words. The transition from cycle M1 to other cycles is explained by the timing diagrams shown in FIG. 2. The invention The device for monitoring the control signals of the microprocessor, containing the microprocessor state word register, cycle decoder, counter, first trigger, three AND elements, four OR elements, OR NOT element, and the output of the first OR element is connected to the summing input of the first the counter, the output of the second element OR is connected to the sync input of the first trigger, the first input of the first element OR, and the synchronization input of the microprocessor state word register are connected to the first synchronization input of the device, the first input The first element AND is connected to the second synchronization input of the device, the output of the second element AND is connected to the installation input in a single state of the counter, the first and second inputs of the OR-NOT element are connected respectively to the first and second information inputs of the device for connecting to the Exit and Confirmation of the monitored outputs a microprocessor, respectively, characterized in that, in order to increase the reliability of the control, a permanent memory block, an encoder, second, third, fourth triggers are inserted into the device, with the fifth and tenth elements are I. the fifth element OR, the element is NOT, the group of information inputs of the microprocessor state register is a group of information inputs of the device for connecting the monitored microprocessor to the data bus, the group of outputs of the state microprocessor word register - cycle encoder, the output group of which is connected to the group of inputs of the encoder, the output group of which is connected to the group of high-order bits of the address input of the memory block, the group of young their bits of the address input of which is connected to a group of outputs of the counter, allowing the input of which is connected to the output of the element OR NOT, the input of the installation in O of the counter is connected to the output of the third element OR, whose first input, the inputs of the installation in O of the first trigger and the status word register the microprocessor is connected to the reset input of the device for connecting to the reset input of the controlled microprocessor, the first output of the cycle decoder is connected to the first input of the second element And, with the inverse first input of the third element I. The first input of the fourth element I. the second input of which and the second input of the second element OR are connected to the second synchronization input of the device, the first output of the fixed memory block is connected by the synchronous input of the second trigger and the first inputs of the fifth and sixth elements And, the second output of the fixed memory block connected by the synchronous input of the third trigger and the first inputs of the seventh and eighth elements And, the third output of the permanent memory unit is connected to the synchronous input of the fourth trigger and the first inputs of the ninth and tenth elements And, the fourth th output of the block of permanent memory connected to the second input of the second element And the second input of the third element And, the output of which is connected to the second input of the third element OR. the inverse of the second input of the first element And allowing input of the microprocessor state word register, the third input of the second element I, the second input of the fifth element I, the installation input O of the second trigger are combined and connected to the third information input of the device for connection to the output of the controlled microprocessor synchronization, the second output of the second trigger the input of the sixth element And the second input of the seventh element And and the first input of the fifth element OR is combined and connected to the fourth information input of the device for connection to the output Receiving information of the controlled microprocessor, the second input of the fifth the OR element is connected to the output of the fourth AND element, the output of the fifth OR element is connected to the installation input in O of the third trigger, the direct output of which is connected to the second input of the eighth AND element, the input of the element is NOT the fifth information input of the device for connection to the output Issuing controlled microprocessor information, the output of the element is NOT connected to the second input of the ninth element I and the installation input in O of the fourth trigger, the direct output of which is connected to the second input of the tenth element AND, the outputs of the fifth, seventh, ninth, sixth, eighth, tenth elements of I are connected respectively, the first to the sixth inputs of the fourth OR element, the output of which is the output of a device error, the inverse information inputs of the flip-flops from the first the fourth is connected to the logical bus O, the direct output of the first trigger is connected to the third input of the first element AND, the output of which is connected to the second input of the first element OR. 30 2B 29 Fig 2 to IT tc if o) when sgprpngl (Ј Aff / 73V F F in D w PI - H . SJ at 5p / usche / sl / to page stfJ. / 73U L P. H1 P D S R D w and BUT and and