SU1432522A1 - Device for shaping an interrupt signal - Google Patents

Abstract

The invention relates to digital computing and can be used in computer systems interruption systems, including control computers and complexes. The aim of the invention is to increase the speed of the device by reducing the reaction time. The device contains six triggers, three shift registers, two majority, elements, four multiplexers, ten And elements, two registers and a comparison circuit. The device combines in time the search for the next request input containing the request with the object of a general interrupt request and setting a limit on the number of polled request inputs, simplifying the reset procedure of the total interruption request and the initial reset procedure of the device. In addition, the device uses an external interrupt mask in parallel with the inner mask jg of aborting and indicates the faulty area of the first memory block in the self-monitoring mode. 1 il. (L

Description

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The invention relates to the field of digital computing and can be used in systems for interrupting computing systems, including control computers and complexes.

The purpose of the invention is to increase the speed of the device.

The drawing shows a block diagram of the device.

The device contains a clock input 1 of the device, input 2 of the reset request for the device has stopped, input 3 starts

The first counter 13, which with a certain frequency receives pulses from the output of the generator 12 pulses, when POM01DI decoder 19 and elements AND 20-22 groups in each step of checking the availability of a request on a group of inputs 5-7 checks the request input of the group whose number coincides with the contents of the higher bits of the first counter 13, which are fed to the input of the decoder 19 from the output of the first counter 13. This test of the query input consists in comparing the values

to reset the device, a group of inputs j5 of the request signal for this request 4 device data, a group of request inputs 5-7 of the device, an input 8 blocking the device, an input 9 prohibiting interruption of the device, an input 10 of the device mode, element 11, generator 20 12 pulses, counter 13 , And 14, Element And 15, Shift Register 16, AND-NOT 17 Element, Multiplexer 18, Decoder 19, AND Elements 20-22 Groups, OR 23, Counter 24, NOT Element 23.25 bits of the first counter 13 and check for the three previous test periods stored in the first memory block 30 with the current value a request signal at the request input and determining whether the value of the request signal changes. If the request signal does not change the value at this request input, then after some time a change of one higher

multiplexer 26, element 27, element 28, trigger 29, memory block 30, element 31, shift register 32, majority element 3, memory block 34, element 35, elements 36 and 37 of modulo two, flip-flops 38-41, parallel register 42, comparison circuit 43, element AND 44, trigger 45, shift register 46, majority element 47, element 48, multiplex 30

is believed to be. next order entry. If a change in the value of the request signal is detected at this request input and the trigger 38 has not previously been set (i.e. there was no general interruption request), the trigger 38 is set, a single signal is set at the device output 58, the signal value is written to register 50 a query on the request gatekeeper 49, register 50, multiplexer 51, 35 (zero bit of register 50) and AND 52, device 52, device tag output 53, device clock output 54, device address output groups 55 and 56, device resolution output 57, signal output 58 set up , the code output group 59 of the device.

The device works in two modes - main and self-control mode. The mode of operation is determined by the signal received at input 10.

When operating in the basic mode, periodic polling of the inputs 5-7 of the device is performed, inputs 5-7 are polled in turn, the last input in the period is a query input that has a sequence number equal to the code entered earlier in register 42, then polling inputs 5-7 is done first.

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Yes, the request input (the remaining bits of the register 50). The values of the request signal and the code of the request input and output of the register 50 are fed to the outputs 59 of the device, later they are used to form the initial address of the interrupt service program. At the same time, the operation of the trigger 39 is resolved, since a zero signal is removed from the reset input of this trigger. Then a change is made to the most significant bits of the first counter 13 and the next in order ordering input of group 5-7 is checked. This completes the search for the next interrupt request with the maintenance of the current common interrupt request.

In case a change is detected in the basic mode, the second multi 55 of the request signal value to the danplexer 26 switches the signal from the Bbf-stroke of the OR element 23 to the trigger input, e-29.

the request signal at this request bit of the first counter 13 and spent over the three pre-validation periods stored in the first memory block 30 with the current value of the request signal at the request input and determining whether the value of the request signal changes. If the request signal does not change the value at this request input, then after some time a change of one higher

is believed to be. next order entry. If a change in the value of the request signal is detected at this request input and the trigger 38 has not previously been set (i.e. there was no general interruption request), the trigger 38 is set, a single signal is set at the device output 58, the signal value is written to register 50 query on the query input (zero bit register 50) and ko0

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Yes, the request input (the remaining bits of the register 50). The values of the request signal and the code of the request input and output of the register 50 are fed to the outputs 59 of the device, later they are used to form the initial address of the interrupt service program. At the same time, the operation of the trigger 39 is resolved, since the zero signal is removed from the reset input of this trigger. Then a change is made to the most significant bits of the first counter 13 and the next in order ordering input of group 5-7 is checked. This completes the search for the next interrupt request with the maintenance of the current common interrupt request.

In case it is detected by a modified request input and the second trigger 38 was previously set, the trigger 39 is set, from the inverse

whose output to the input element And 1 is given a zero signal that prohibits the passage of pulses from the clock input 1 through the element 11 to the input of the generator 12 pulses, which fixes the state of the first counter 13. After resetting the trigger 38, the trigger 39 is reset. from the clock input 1 through the element 11 to the input of the generator 12 pulses. Next, a flip-flop 38 is set, a single signal appears at output 58, register 50 requests the input request signal and the request input code, etc., as described above.

Checking the request inputs to form a general request for failure at the output 58 of the device consists in comparing the request signal of a specific request input over the three previous verification periods stored in the first memory block 30 with the current value of the request at this request input and determining whether the value changes request signal. According to the first operation of the first block of 30 memory as part of the device.

The first memory block 30 is a operative memory (RAM) with the organization of 1 bit of x words.

In the memory block 30, each request input is assigned a zone of four one-bit words, going further one by one. The zone of the memory block 30 is determined by the higher bits of the counter 13, its number coincides with the number of the request input.

During the search period for all the request inputs, the check of the request value is performed in the standard check cycle. During this check cycle, one operation is performed to write information to memory 30 and three operations to read the information from memory 30 in random order. The reference to the four words of the zone of the memory block 30 is accomplished with the help of two lower bits of the counter 13. This reference to the words of the memory block 30 is performed in turn, i.e. to the first word of the zone, further to the second, third and then the fourth word. For which word of the memory block 30 the information recording operation is executed, determines the control information received from the multiplexer 18 to the control input of the memory block 30.

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For this search period, all the query inputs have the same word number in the zone of the memory block 30 to which information is recorded. At the end of the search period, this number changes cyclically, i.e. ecjm, in the given search period, the record is made into the zone word of memory block 30, the next period, the information is recorded into the word zone one, and after two more search periods, again into the zone word, the number is typed, and so on.

The word number of the zones of the memory block 30 into which information is recorded. This data is formed by the joint operation of the shift register 16, the NAND 17 element and the multiplexer 18. The gate input of the shift register 16 receives a gate generated by the trigger 45, the signal edge of this gate is written to the shift register 16. All outputs of the shift register 16 are interconnected via an AND-HE element 17, the output of which is connected to the serial input of the shift register 16. Therefore, as long as one of the outputs of shift register 16 has a zero signal, single signals are recorded in it. After three search periods for all the request inputs, the AND-NOT element 17 is switched, after which, during the search period, the output of the AND-NE element 17 is a zero signal, which is then written to. register 16 shift. Thus, the ZERO signal is located only on one of the outputs of the shift register 16 or at the output of the NAND element 17. The output of the NAND element 17 corresponds to all the first words of the zones of the memory block 30. The three outputs of the shift register 16 correspond to all the second, third and fourth words of the zones of the memory block 30, respectively. The interrogation of the outputs of the register 16 shift and entry element IS-HE 17 performs multiplexer 18, on the control input of which two lower bits of counter 13 arrive, In accordance with the state of lower bits of counter 13, the output of multiplexer 18 appears A flag indicating the type of operation of the memory block 30 is writing or reading.

The address of the word address in memory block 30 is formed by combining

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junior and senior order counts for previous periods

13. tests from the output of memory block 30 in

The shift test of the change in the shift register 32 is performed in the query at the request input in this three scheduling information, the search information period is the same for all zones from the memory block 30. Control

of the memory block 30 and consists of filing information into the register 46 of the transmitter code of the request input to the descrambler from the output of the memory block 30 provide 19, the address inputs of blocks 30 and 34 pack the element I 52, multiplexers

mti and register 50, write operations 18 and 51. Multiplexer 51 providing the current value of the request to quit polling the outputs of register 16

the element OR 23 through the multiplexer of the output element AND-NOT 17 in another direction 26 to the trigger 29, four operations of the sequence than the multiplexer

rascheni to block 30 of memory, three one-18, i.e. starting from the third exit

There are two ways to write the values of the request for tri-register 16 shift, then to poll the previous checkout period for the output of the AND-NOT element 17 and the remaining 32 shift, for two write operations, the shift register 16 outputs. Request data for the two previous periods from the multiplexers 18 and 51

The check codes in the shift register 46 are fed to the inputs of the AND 52 element, which

Signal Comparison operations request two gates to be omitted.

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for the four verification periods with the help of the recording for the clock at the input of the register of the major elements 33 and 47 and the ele-shift; as a result of this modulo-two addition operation 36, onerTs of recording the value of the query for Recording the common signal of the preamplifying test periods from the output from the output of the multiplexer 49, BTpnr-jg of the memory block 30 to the register 46, headers 38 and 39. are connected during two of the three operations - Strobe information recording in the trigger of information reading from the first 29 is formed by the element And 28 on the cos-block 30 of the memory.

the fall of two inverse sig-values. After a couple of operations of inverting the lower bits of the counter 13 to the memory unit 30, a strobe operation is performed on the first record of the request signal in the output of the generator 12 pulses. Since you are this block, which ensures the use of the second element AND 28 strobe, the request value is sent to the next clock input of the trigger 29. the next test periods; In register 32, the trigger 29 fixes the value — there is a three-bit word, the content of the request, sent to its instantaneous value of the request for the three preliminary input from the output of the multi-leading test period, and to the register-plexer 26, for the whole search cycle. The shift shift is a two-bit word. This provides the possibility of asin-containing query values for two time-consuming sources of queries that precede verification periods; taps and devices. To provide front output Information from the trigger output 29 or cut the signal against the background of single input information block or group interference is used poppy memory 30 and the input majoritarian elements 33 and 37. On the first element 47. This information is recorded the input of the second major is sent to the memory block 30 when ment 47 receives the output information from the output of the multiplexer 18 receives the trigger 29, the two other inputs write to the memory block 30. After recording the value of the request for information from the output of shift register 46. trigger 29, there are four one-informations from three bits of the register of access to memory block 30, 32 shifts go to three inputs each of which is accompanied by a primitive element 33. Information is written or shared with a sign from the outputs of the majority elements 33 by the multiplexer 18. This and 47 is compared by the first element, the attribute also arrives at the second modulo-36 addition, which is input of the AND element 31, while the ban 55 generates a signal 1 at the output and writes information in the register ah and 32 shear during the write operation; On the coincidence signal. The signal is in memory block 30. Thus, the modulo-two operation of the output of the addition element 36 indicates the presence of a front or a slice of a signal at the polled request input and the need to form a general interrupt request.

The memory unit 34 is a permanent storage device with the organization of 1 bit X P words. This block contains the signs of permitting the forcing of a general interrupt request on the front or slice of the request signal, i.e., the mask is applied. The operation of memory 34 can be disabled by a signal at input 8. To do this, a signal 1 is set at input 8, which causes the appearance of a single signal at the output of memory 34 and the resolution of generating a common interrogation request. If the O signal is set at input 8, an internal masking mask is generated.

The address of accessing the word of the memory block 34 is formed by the merging of the higher bits of the counter 13 and the information at the output of the majority element 47. In the block 34, the word corresponding to this memory zone of the block 30 and the request value received from the majority element 47 are stored (1) if the formation of a general request is allowed, and a Ban (O) otherwise.

Element 35 generates the value of the interrupt signal, which through multiplexer 49 enters the information inputs of the flip-flops 38 and 39. The strobe of recording information in triggers 38 and 39 is formed by the element 14 and the ninth element 48. The element 14 forms at its output a strobe by coincidence single signals at the lower bits of the counter 13 and the gate present at the fourth output of the generator 12 pulses, provided that the trigger 41 is set, i.e. its output signal is 1. Element And 48 forms a strobe at the output if a single signal is installed at input 8. Trigger 38 is set up by slice the signal at the output of the ninth And 48 element. Trigger 39 is set at the front of the signal at the output of the And 48 element. Trigger 39 is set at the front of the signal at the output of the And 48 element. Triggers 38 and 39 from different fronts of the strobe provide combination of appearance

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a general interrupt request with a search for the next request input for which a general terminating request will be generated. When installing the trigger 38, the installation of the trigger 39 is enabled, since the signal from the direct output of the trigger 38 is fed to the reset input of the trigger 39 and, since this signal 1, its installation is permitted. Previously, the trigger 38 was reset and, due to the priority of the reset input, the installation of the trigger 39 by the signal O at the input Reset trigger 39 was prohibited.

When a flip-flop 38 is installed, a common interruption request is generated at its output, arriving at the device output 58, and on the front of this signal, register 50 records the request input code and the value of the request signal at this input against the background noise. Signals from the output of register 50 arrive at the outputs 59 of the device, while the code of the request input containing the request of the alarm is recorded for the time of the interrupt request processing program.

If a flip-flop 38 is installed, and a single signal is output at the output of multiplexer 49 during the strobe at the output of AND 48, the flip-flop 39 is set and prohibits the passage of clock pulses through AND 11. This fixes the code of the next request input containing the interrupt request for subsequent writing to parallel register 42 after processing the previous general interrupt request from another request input.

To reset (zero out) the total, the signal 1 de 1 is applied

Ger 40, the output signal U at the inverse output of which passes through the element 14, completes reset of the trigger 38 and register 50, and also prohibits the passage of pulses of the clock frequency through the element t1, which ensures that the following requests are not lost at the request inputs of the device signal delay Reset at input 2 5 reset interrupt request.

When power is turned on, device nodes are in an undefined state. Therefore, the input 3 comes

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millet grill on entry 2

, the pulse is set at the input of the pulse

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signal O, which resets binary counters 13 and 24, triggers 38-41 and 45, registers 50 and 42. When resetting trigger 41 to four search periods, the formation of gates at the output of the AND 15 Ij is blocked, therefore, the formation of a common interrupt request is blocked. At the same time, data is reliably recorded in memory block 30, as well as device performance increases due to a more accurate linking of the beginning of the formation of a general interrupt request to the time of completion of memory block 30 and completion of the transition process at device request inputs 5-7. .

To reduce the search period and, consequently, improve the performance of the device, setting the level of polled query inputs is used. At the same time, the time spent on polling the interrogation is excluded: the inputs whose codes exceed the established level. For this, register 42, circuit 43, AND 44 and trigger 45 are used.

After the initial reset signal has been sent to reset input 3, trigger 41 is reset and register 42 is reset. After trigger setup 41, data is written that is present 1x at input 4 to register 42. Data is the binary code of the last polled request input of the group of request inputs 5-7 . The data is recorded in register 42 on the signal front at the first speed of the generator 12 pulses. Data change is recommended when there is a low-level signal at output 53, since this guarantees the absence of false general interrupt requests. The code of the polled request inputs is removed from the outputs of register 42 and fed to the second group of inputs of the comparison circuit 43, the first group of which receives signals older bits of the counter 13. If the signal codes on the first and second groups of inputs coincide, the circuit 43 generates a signal 1, if it does not, the signal O. If there are signals 1 at the outputs of the lower bits of the counter 13, the first output of the pulse generator 12 and the circuit 43 is allowed to set in one state the trigger 45-, since at its reset input and in0

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the formational input signal is received 1. The trigger 45 is set to one state by cutting the signal at the second output of the generator 12 pulses, in this case the counter 13 will be reset and the data will be written to the shift register 16. The trigger 45 is set, driven to the zero state by a cut of the signal at the first output of the generator 12 pulses.

In a number of tasks of building interrupt systems, in addition to the internal interrupt mask formed by g memory 34, it is required to form an external interrupt mask prohibiting the formation of a common interrupt request for certain request inputs, groups of request inputs or all request inputs of a device. For this, interrupt input 9, device address outputs 56 and 55, and device output 57 are used. The prohibition signal is applied to the interrupt input 9 in accordance with the zone address of the memory block 30, where the signal values of the request input and the value of the signal on this request input are stored in the same way as the mask is formed by the block

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When operating in self-monitoring mode, the device operates as follows. To the input 10 of the mode, the unit triggers 1, which sets the self-control mode, switches the multiplexers 26 and 46 to switch the reference information,.

In this mode, the multiplexer 26 prohibits the passage of the signal from the output of the element OR 23 to the input of the trigger 29 and allows the transfer of the reference signal from the first output of the counter 24 to the input of the trigger 29.

Now the device generates a signal of failure at the output of the element AND

35 in accordance with the reference, periodically changing polarity, signal at the first output of counter 24, which serves as a simulator of input signals

on the request inputs of the device. 0

Claims (1)

Invention Formula A device for generating a signal of breaking, containing element 5 NOT, seven elements AND, two counters, a decoder, a group of elements AND, an IL element, a clock pulse generator, three triggers, two memory blocks. D 0 five eleven two shift registers, the NAND element, two multiplexers, the first major element, two modulo two addition elements, the first input of the first element I connected to the clock input of the device, the outputs of the higher bits of the first counter connected to the inputs of the decoder, the first the group of address outputs of the device, with the first group of inputs of the address of the first and second memory blocks, the overflow output of the first counter is connected to the counting input of the second counter, the outputs of the low bits of the first counter are connected to the corresponding inputs By the second element And, with the second group of inputs of the address of the first memory block and with the address inputs of the first multiplexer, the first output of the pulse generator is connected to the first inputs of the third element And, the inverse outputs of the lower bits of the first counter are connected to the corresponding inputs of the third element And, the second output generator The pulses are connected to the clock input of the first memory block, the third output of the pulse generator is connected to the second input of the second element AND, each output of the decoder is connected to the first input of the same name AND group element, the second inputs of the AND group elements are connected to the corresponding request inputs of the device, the outputs elements AND groups are connected to the inputs of the element OR, the output of the third element I is connected to the clock input of the first trigger, the output of the first trigger is connected to the information input of the first memory block, the output of the first block a memory coupled to the data input of the first shift register pervm, second and third outputs of the second shift register are connected , with the first, second and third inputs of the NAND element, with the first, second and third information inputs of the first multiplexer, respectively, the output of the NAND element is connected to the data input of the second shift register and the fourth information input of the first multiplexer, the output of the first multiplexer is connected to the recording control input of the first block of the input of the first addition unit modulo two, the output of the second memory block is connected to the first input of the fourth element I, the output of the first addition element modulo two is connected to the second input of the fourth element I, the output of the second trigger is a signal output device 5 ten 15 20 25 thirty 35 40 45 50 va, the first input of the first element I with the same input of the initial reset of the device, the control input of the second multiplexer is connected to the input of the device mode, the first bit output of the second counter is connected to the nepBbfi i information input of the second multiplexer, the output of the OR element is connected to the second information the input of the second multiplexer; the output of the second multiplexer is connected to the formation input of the first trigger; the second discharge output of the second counter is connected to the input of the HE element; the third discharge output of the second counter is connected It is not connected with the first input of the sixth element And, the output of the element is NOT connected to the second input of the sixth element And, the output of the sixth element And is connected to the first input of the second element of the modulo two, the output of the fifth element And is connected to the reset input of the second trigger, characterized in that, in order to increase the speed of the device, quarter, fifth and sixth triggers, the third register of the shift, the second major element, the third and fourth multiplexers, the first, the ninth and ten elements are entered into it, and the first and second registers and schema, The clock input of the third trigger is connected to the clock input of the device, the output of the first element is connected to the start input of the pulse generator, the outputs of the higher bits of the first counter are connected to the group of information inputs of the first register and the lower bits of the first counter connected to the address inputs of the third multiplexer, with the corresponding inputs of the eighth And element, and are the second group of address outputs of the device; the first output of the pulse generator the outputs of the first shift register are connected to the counting input of the first m ti connected to the inputs of the first major element, the output of the first major element is connected to the first counter, with a clock input of the second register and with the corresponding input of the seventh element And, a quarter output 32522. 12 the input of the first addition element modulo two, the output of the second memory block is connected to the first input of the fourth element I, the output of the first addition element modulo two is connected to the second input of the fourth element I, the output of the second trigger is a signal output device 5 va, the first input of the fifth element I is connected to the input of the initial reset of the device, the control input of the second multiplexer is connected to the input of the device mode, the first bit output of the second counter is connected to the nepBbfi i information input of the second multiplexer, the output of the OR element is connected to the second information input of the second the multiplexer, the output of the second multiplexer is connected to the information input of the first trigger, the second discharge of the second counter is connected to the input of the element HE, the third discharge of the second counter connected to the first input of the sixth element And, the output of the element is NOT connected to the second input of the sixth element And, the output of the sixth element And is connected to the first input of the second addition element modulo two, the output of the fifth And element connected to the reset input of the second trigger, that, in order to increase the speed of the device, the fourth, fifth and sixth triggers, the third shift register, the second major element, the third and fourth multiplexers, the eighth, ninth and ten elements AND, the first and second registers and This is the third comparison, the clock input of the third trigger is connected to the clock input of the device, the output of the first element I is connected to the start input of the pulse generator, the outputs of the higher bits of the first counter are connected to the group of information inputs of the first registerr, the outputs the lower bits of the first counter are connected to the address inputs of the third multiplexer, with the corresponding inputs of the eighth AND element, and are the second group of address outputs of the device, the first generator output Pulse connected to the counting input of the first counter, with a clock input of the second register and with the corresponding input of the seventh element And, a quarter output the pulse generator is connected to the first inputs of the eighth and ninth elements, the output of the first trigger is connected to the first input of the second major element, the output of the first memory block is connected to the information input of the third shift register, the first, second and third outputs of the second shift register are connected to the first, the second and third data lines of the third multiplexer, the output of the NAND element is connected to the fourth information input of the third multiplexer and is the output of the device attribute, the output of the first multiplex The lexor is connected to the second inputs of the eighth and ninth elements, and the output of the third multiplexer is connected to the third input of the ninth element, and the output of the first addition element in module two is connected to the second input of the second element modulo two, the output of the second trigger is connected to the reset input the fourth trigger and the clock input of the first register, the control input of the fourth multiplexer is connected to the device mode input, the read control input of the second memory block is connected to the device lock input, the second bit The second output of the second counter is connected to the clock input of the fifth trigger, the output of the fifth element is connected to the reset input of the first register, the outputs of the first register are the code group of the device outputs, the output of the ninth element is connected to the clock input of the third shift register, the output of the eighth element And connected to the clock input of the first shift register, the output of the third shift register is connected to the second input of the second major element, the output of the fourth element I is connected to the first information input of the fourth cartoon iplexer, the output of the second element modulo two is connected to the second information input of the fourth multi0 five five 0 five 0 five the plexer, the output of the fourth multiplexer is connected to the information inputs of the second and fourth triggers, the inverse output of the fourth trigger is connected to the second input of the first element And, the output of the second major element is connected to. the second address input of the second memory unit, with the second input of the second addition unit modulo two, with the corresponding input of the information group of the first inputs of the first register, is the device enable input, the interrupt reset input of the device is connected to the information input of the third trigger, the output of which is connected to the third input of the first element I and to the second input of the fifth element I, the reset input and the information input of the fifth trigger, the first reset input of the first counter and the reset input of the second counter connected to the input ohm initial reset the device, the output of the first flip-flop is connected to the third input of the second element And to the reset input of the second register, the output of the second element And is connected to the first input of the tenth element And, and is the device clock, the input of the device interrupt disable is connected to the second input the tenth element And, the output of the tenth element And is connected to the clock input of the second trigger and the clock input of the fourth trigger, the group of data inputs of the device is connected to the group of information inputs of the second register, output The second register is connected to the second group of inputs of the comparison circuit, the output of the comparison circuit is connected to the third input of the seventh element AND, the output of the seventh element AND is connected to the reset input and the information input of the sixth trigger, the output of the sixth trigger. Hera is connected to the clock input of the second shift register and the second reset input of the first counter, the clock input of the sixth trigger is connected to the second output of the pulse generator. L /