SU813504A1 - Device for retrieval of addresses from storage units - Google Patents

Description

The invention relates to computer engineering and is intended for organization sequential addressing of memory cells at a random time moving ob- _ Applications za- ^e pis and reading, in particular can be used in the buffer memory storage devices.

Known devices for fetching addresses from memory blocks containing ^υ address counters for writing and reading, a reversible counter for determining the difference of codes for write and read addresses and elements And T11 And G2]. fifteen

The disadvantage of these devices is that in the event of an accidental failure of the reverse counter, false information is stored, which leads to the malfunctioning of only 20 devices, since it does not have the ability to self-repair the correct functioning.

Closest to the proposed device is a device containing address * 5 counters for writing and reading and a comparison element, the inputs of which are connected σ 'by the corresponding output buses of the address counters, the counting inputs of which are connected to the control bus 30, and their reset inputs to the bus reset [3].

However, in such a device, with each change of the write address or read address, it is necessary to compare them by more, less and equal. The operation execution time is more or less proportional to the number of bits η of the compared codes and is equal to η · ΐ, where € is the duration of the transient process in one bit of the comparison element. In addition, the three-step comparison element is quite complex.

The purpose of the invention is improving performance and simplifying the device.

This goal is achieved in that the device contains two And elements, two differentiating elements and a trigger, the installation input of which is connected through the first differentiating element to the output bus of the upper bit of the address counter of the record, the first reset input of the trigger through the second differentiating element is connected to the output bus of the senior bit of the address read counter, the second trigger reset input is connected to the reset bus, the direct trigger output is connected to the first input of the first AND element, the output of which is connected to the bus, PETA recording inverse output latch coupled to the first input of the second AND gate, whose output is connected to the bus reading prohibition, and the second inputs of AND gates connected to the output of the comparison element.

The drawing shows a block diagram of the proposed device.

The device contains an address count · record 1, control bus 2 for supplying pulses for changing the write address, address counter 3 for reading, control bus 4 for supplying pulses for changing the read address, element 5 for comparison, differentiating elements 6 and 7, trigger 8, elements 9 and 10 , a write inhibit bus 11, a read ban 12, and a reset bus 13.

The device operates as follows.

After power-up, both address counters and the trigger on the reset bus are reset to zero. In this case, the comparison element indicates the equality of counter codes, and a signal corresponding to a logical unit appears at its output. The same signal is present at the inverse output of the trigger. As a result of the coincidence of the signals of logical units at the inputs of the And 10 element, a read-out signal is generated at its output, indicating that · the information is not contained in the memory. After the information has been written to the memory at the zero address, the pulse of the change of the recording address is received at the counting input of the address counter of the record and the counter forms the next record address, which differs by one. The inequality of the address codes is indicated by a comparison element and a signal corresponding to a logical zero appears at its output and a read ban signal is removed. If reading now happens, then the read address code will change by one. The codes of the write address and the read address will again become equal, which will entail the re-formation of the read ban signal. In subsequent readings and readings, the address codes will increase, however, the read address code will not be able to get used to the write address code, which avoids reading at the addresses of memory cells that do not contain information.

Each of the address counters is a summing counter with a conversion factor of 2 ^P. The arrival of the 2 ^n- th pulse of the address change per ^hour writes the write address counter to zero, and the write address code becomes less than the read address code. When the address recording counter goes to zero, a transfer signal is generated on the output bus of the high-order bit of the counter, and the pulse arising from the output of the differentiating element 6 sets the trigger to unity ·: state. If the write address code continues to increase, then at the time of its equality to the read code at the inputs of the And 9 element, the signals of the logical units from the output of the comparison element and the direct output of the trigger will coincide, which will lead to the formation of a write inhibit signal. If then reading takes place, the comparison element, having determined the inequality of the address codes, will generate a signal corresponding to zero at its output, which will lead to the removal of the write prohibition signal. Thus, now the write address cannot become larger than the read address, which prevents writing information to the addresses of memory cells from which information has not yet been read.

Upon receipt of a 2 ^n- th pulse of a change in the read address, the address read counter will return to zero and from then on the read address code should remain less than the write address code, for which the pulse generated from the transfer signal of the read address counter by the differentiating element 7 brings the trigger to the state in which a signal corresponding to a logical unit appears at its inverse output, and in case of equality of the address codes at the output of AND element 10, a read inhibit signal appears.

The economic effect of the device is determined by its simplicity and speed.

Claims (3)

1. USSR author's certificate No. 427379, cl. G 11 C 11/00, 05.05.74, 2.Voytenko Yu.G. and others. The control unit of the buffer memory of a scanning automaton. Dubna, 1970. 3. Buzunov Yu. A., Vavilov E., N. Principles of construction of control computers. Kiev, 1972, p.218 (prototype).