RU1803919C - Device for processing messages - Google Patents

Abstract

The invention relates to computer technology and can be used in the construction of computer systems for processing large amounts of data belonging to different classes of objects. The purpose of the invention is to increase the speed of the device. This goal is achieved in that the device contains a clock, nine triggers, seven OR elements, an input register, a comparison node, three counters, eight AND elements, an OR-NOT element, three AND-NOT elements, a delay element, four memory blocks These two elements are NOT, control unit, output register. 3 ill.

Description

The invention relates to computer technology and can be used in the construction of computer systems for processing large-volume data belonging to various classes of objects.

The purpose of the invention is to increase speed by organizing group parameters.

In FIG. 1.2 shows a block diagram of devices; in FIG. 3 is one example of a control unit implementation.

The device contains a clock generator 1, triggers 2-6, AND elements 7-9, OR elements 10-13, OR element NOT 14, AND elements NOT 15, comparison unit 16, counter 17, register 18, memory unit 19 , control unit 20, counters 21 and 22, information input 21, device outputs 23 and 24, device mode input 24, device control inputs 25 and 26, triggers 27-30, AND elements 31-35, OR elements 36-38, NAND elements 39 and 40, NAND elements 41, 42, memory blocks 43, 44, output register 45, delay element 46, counters 47 and 48, memory block 49, device outputs 50-54, initial input 55 comp of the device.

The control unit 20 comprises a multiplexer 56, a counter 57, the first in the second AND-NOT elements 58 and 59, the OR element 60, the trigger 61, the And 62 element, the first in the second pulse formers 63 and 64.

The code coming from the output of counter 17 to the address inputs of block 19 causes the appearance of an N-bit word at its outputs containing 1 - (N -1) bits — object code; IM th bit - a sign of a ban on writing. If the Nth bit of a word is equal to a logical unit, then the recording of information on all parameters of this object in the block 49 of the memory is prohibited. At the same time, the code from the output of counter 17 goes to the higher ones

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bit address inputs of blocks 43, 44 of the memory and determines the base address of the sample for the selected object. The low-order bits of the address inputs of the memory blocks 43 and 44 receive a code from the control block 20, which determines the choice of descriptors for a particular parameter of the selected object. Each parameter is characterized by two descriptors: the write address of the selected parameter (stored in memory block 43) and the length of the parameter record (stored in memory block 44). By parameter recording length is meant the number of information recording units defined for a given device (e.g., byte - 8 bits; word - 16 bits).

The delay time of the passage of the signal through the element 46 is chosen so as to ensure reliable recording of the information selected from the main memory unit 49 into the output register 45.

The shaper (63, 64), when a potential difference from zero to a unit level appears at its input, generates a single pulse of a single level at its output.

The memory unit 49 is designed to store information that can change its value over time. The information unit of recording / reading of block 49 is a message (byte, word), the address of which is determined by the code coming from the output of counter 47 of the write address to the address inputs of block 49 of random access memory.

The structure of the information recorded in the block 44 of the memory is as follows: 1 - (M - 1) bits - the length code of the corresponding parameter of the selected object in units of

letters specific to a particular

devices M-th category - a sign of the prohibition of recording information on this parameter of the selected object, if it is equal to a logical unit. If the length code of the corresponding parameter of the selected object is zero, then it is considered that this parameter of the object is not defined in the device (absent),

If the output 51 of the device is in the READY-1 single state, this is a sign of the device's readiness to perform another operation or to service another message.

The device operates as follows.

In the initial state, after a single level RESET signal is received at input 55 of the device, triggers 2, 3, 4, 6, 28, and 30 are in the zero state, triggers 5, 29, 27 are set to single state 5 0 15

0

5

0 5

0

5

0

5

counters 17, 47, 48 are reset to zero, the outputs of the zeroing indicators 17, 48 are in single state, signals READ 1, RECORD 1, CONTINUE 1, SELECT OBJECT O, PROHIBIT RECORDING OBJECT O, START O, RECORDING OF PARAMETER O, END OF SELECTION OF OBJECT O, READY 1, PROHIBITION OF RECORDING OF PARAMETER O, SELECTION BY PARAMETERS, PARAMETER IS NOT DEFINED.

The device operates in two modes: WRITE, READ.

In the RECORD mode, a message containing the object code is received at the information inputs of the device 21. At the same time, a short-term zero-level RECORDING signal is received at the device input 26, which ensures that the triggers 2, 3 are set to the single state, the trigger 27 is reset to the zero state READY 0, the message is recorded from the information inputs of the device 21 to the input register 18. The trigger 2 goes to a single state allows the passage of clock pulses from the generator 1 to the counting input of the counter 17, When changing the value of the counter 17 to the first information inputs of the comparison node 16, messages stored in the block are sequentially received In the 19th memory, without taking into account the senior M-bit (sign of a write prohibition), they are compared with the message located in the input register 18. In this phase of the device’s operation, three situations are possible:

1. In the block 19 of the memory there is no message (object code) identical to the message in the input register 18. At the same time, after the counter 17 completes the complete counting cycle at the output of the node 16, the logical unit signal is not generated and the sign of resetting the counter 17 appears at the output a difference in the signal from zero to a unit level, which causes the trigger 27 to be set to a single state, resetting triggers 2, 3 to a zero state. Moreover, the message in the memory unit 19, determined by the zero state of the counter 17, is not identical among the messages arriving at the information inputs of the device 21. The passage of clock pulses from the generator 1 to the counting input of the counter 17 is stopped. The outputs 23, 22 of the device remain in the zero state. SELECTION OF OBJECT O, PROHIBITION OF RECORDING OF OBJECT 0, and output 51 - TOTOV 1, this is a sign that the object code in the message recorded in register 18 is not defined in memory block 19 . The device is ready to analyze the following object code.

2. The code of the register object 18 is the same as the message object code of the memory unit 19, however, the Nth bit of this message is a logical unit. In case of coincidence of the messages arriving at the information inputs of the comparison unit 16 from the memory unit 19 and the register 18, a potential signal drop from the zero to the unit level is formed at the output of the node 16, which resets the trigger 5 to the zero state. In this case, after the counter 17 completes the complete counting cycle at: the sign of zeroing of the counter 17 is output, the signal drops from zero to a single level, which causes the trigger 27 to be set to a single state, resetting triggers 2, 3 to a zero state. The outputs 23, 22, 51 of the device go into a single state. SELECTION OF OBJECT D:: PROHIBITION OF RECORDING OF OBJECT 1, READY - 1, which is a sign that the object code in the message recorded in register 18 is defined in memory block 19 , but the recording of information on all parameters of this object in the block 49 of the memory is prohibited. The device is ready to analyze the next iodine of the object.

3. The code of the register object 18 is the same as the code of the message object of the memory unit 19 and the NJth bit of this message is logical zero. If the messages arriving at the information nodes 16 of the comparison from the memory block 19 and the register 18 match, at the output of the node 16 you form a potential signal difference from zero to the unit level, which ensures: setting the triggers 6, 5 to the unit state, reset trigger 2 to zero state, blocking the passage; write, read signals to the input of setting trigger 2 to the single state blocking the passage of the signal LOCK to the inverse input of setting trigger 3 to the single state, setting the trigger 27 in unit e state. The outputs 23, 22, 51 of the device B (OBJECT 1 BOR, PROHIBITION OF OBJECT RECORDING, READY 1 are the fact that the object code in the message recorded in register 18 is defined in memory unit 19 and information is recorded - or all parameters of this object are allowed in the memory block 49. The device is ready to continue working and comes to life after entering the next message, which indicates the parameters of the selected object that are included in the Write / Read operation.

The procedure for finding the required object specified in the message recorded in

input register 18, among the messages of the memory unit 19 in the READ mode, it is carried out in the same way as in the REC mode, except that it is performed under the control of the READ signal and does not check the condition of the write ban on all parameters of the object (trigger 3 by the signal zero READ level is not set to a single state). 0 In the next phase of the operation of the device, a message containing information on those parameters of the selected object that are included in the ongoing operation is received at the information inputs 21. At the same time, at the input 26 of the device, a short-term zero-level RECORD / READ signal is received, on the leading edge of which a message is recorded in input register 18, the trigger 27 is reset to 0, the state is READY 0, and on the trailing edge, the trigger is set 4 to a single state. The START 1 signal blocks the passage of the RECORD (READ) signals to the input of the register register 18 and enters 5 to the control unit 20. For the sake of clarity, we will consider a specific message recorded in register 18 in binary code 10000011, which indicates that the first, second, and eighth parameters of the object selected in the first phase of operation are included in the operation RECORDING (READING) 0.

Prior to receiving the START signal 1, a zero code 5 is set at the output of counter 57, which ensures the formation of: at the output of multiplexer 56, the state of the least significant bit of the message recorded in register 18, at the output of the initial recording address memory block 43 in the first memory block 49 0 th parameter of the selected object; at the output of the memory unit 44 (the number of recording bytes) of the first parameter of the selected object. In this particular case, the logic unit 5 signal is set at the output of multiplexer 56. Upon receipt of the START signal 1, shaper 64 is started, generating a short-term pulse of a unit level. RECORDING OF PARAMETER 1. On the leading edge of the signal ZA-0, RECORDING OF PARAMETER 1, the address and length of the first parameter of the selected object are recorded respectively in counters 47, 48. Assume that the first parameter is not defined in the device, then the counter 48 is written 5, a zero code is written and a high signal level is held at the corresponding output of the sign of resetting the counter 48. Then, on the trailing edge of the RECORDING of PARAMETER 1 signal, the trigger 30 transitions to the single state, the trigger 29 is held in the single state, the trigger 28 is in the zero state, and the trigger 27 transitions to the single state. The status of the device outputs SELECTION OF OBJECT 1, PROHIBITION OF RECORDING OF PARAMETER O, PARAMETER. NOT DEFINED 1, READY 1 is a sign that the first preset parameter of the selected object is not defined in the device and the further operation is WRITE (READ) by this parameter impossible.

To continue the operation of the device, a short-term signal is CONTINUED to 0 level zero, on the leading edge of which it is carried out: resetting trigger 27 to the zero state, generating a potential signal difference from zero to the unit level, which enters the counting input of counter 57. The trigger 61 remains in a single state, since a high-level signal from the output of the counter overflow sign 57 is received at its information input. A single code from the output of the counter 57 provides the formation of: leksora 56 state of the second discharge messages recorded in the register 18, the output unit 43 memory addresses starting recording at block 49 the memory of the second parameter of the selected object on the memory length 44 is output (the number of write bytes) of the second parameter of the selected object. In this particular case, a logic unit signal is set at the output of multiplexer 56. On the trailing edge of the signal, CONTINUE 0 is carried out: the driver 64, which generates a short-term pulse of a single level, RECORDING OF PARAMETER 1. On the leading edge of the signal RECORDING OF PARAMETER 1, the address and length of the second parameter of the selected object are recorded respectively in counters 47, 48. Suppose that the second parameter is defined in the device, but in the format of the message recorded in the memory unit 44, the high order bit is logical unit - a flag is set to prohibit recording information on the second parameter of the selected object. Then, a code other than zero is written to counter 48, and a signal level of zero appears at the corresponding output of counter zeroing indicator 48. On the trailing edge of the signal, RECORDING OF PARAMETER 1 switches trigger 30 to zero, holding trigger 29 in a single state state, since a high-level signal is received at its information input (for the REC mode), the transition of triggers 28.27 to the single state. The status of the device outputs SELECTION OF PARAMETER 1, PROHIBITION OF RECORDING OF PARAMETER 1, PARAMETER IS NOT DEFINED 0, READY 1 is a sign that the second set parameter of the selected object is defined in the device, but the RECORD operation on this parameter is impossible due to the set sign of recording prohibition information on the second parameter.

To continue the operation of the device, a short-term signal is CONTINUED 0 of zero level, which generates at the output of multiplexer 56 the state of the third bit of the message recorded in register 18. In this particular case, a logic zero signal is set at the output of multiplexer 56, which allows the passage of clock pulses to the counting counter input 57. Since the parameters 3-7 of the selected object are not included in the operation, then in the process of receiving four clock pulses to the counter input counter 57 at the output of multiplexer 56 is held logic zero state signal, wherein the trigger 61 is held in a logic one state, the signal recording Parameter 1 is not formed. On the leading edge of the fifth clock pulse, the trigger 61 remains in the single state and at the output of the multiplexer 56 a logical unit signal is generated - the state of the eighth bit of the message recorded in register 18, which provides: start of the driver 64, which generates a short-term pulse of a unit level RECORDING OF THE PARAMETER 1. At the trailing edge of the fifth clock pulse at the output of the overflow sign of the counter 57, a signal transitions to the zero state. On the leading edge of the RECORDING OF PARAMETER 1 signal, the address and length of the eighth parameter of the selected object 16 bits long are recorded in counters 47, 48, respectively. The parameter is written in portions of 1 byte per operation. A parameter length code of 2 is recorded in counter 48, and a signal level of zero appears at the output of the reset flag of counter 48. On the trailing edge of the RECORDING OF PARAMETER 1 signal, triggers 29, 28, 3Q go to the zero state, and trigger 27 to the single state. The status of the device outputs SELECTION OF OBJECT 1, PROHIBITION OF RECORDING OF OBJECT O, SELECTION OF PARAMETER 1, PROHIBITION OF RECORDING OF PARAMETER O, PARAMETER IS NOT DEFINED O, READY 1

is a sign that the eighth predetermined parameter of the selected object is defined in the device and the selection of information on it is allowed. The information inputs 21 of the device receive the first 8 bits of the parameter value, the zero-level RECORD signal 26, which resets the trigger 27 to the zero state READY 0 and goes to the write enable input of the memory unit 49. The RECORD signal records 8 bits of the parameter value to block 49 at the address determined by the contents of the counter 47, and generates a short-term zero level signal at the output of the And 34 element, from which the unit is subtracted from the zero to the unit level and the unit is subtracted from the contents of the counter 48 lengths, adding a unit to the contents of the counter 47 of the recording address, setting the trigger 27 to the single state READY 1, which is a sign of the device's readiness to record the next piece of information in the memory unit 49. The second piece of information is recorded in the same way, except that after subtracting a unit from the contents of the counter 48, a logic unit signal is generated at its output of the reset flag, which puts the trigger 29 in a single state. The status of the device outputs SELECT OBJECT 1, PROHIBITED RECORDING OF OBJECT O, SELECT PARAMETER O, PROHIBIT RECORDING OF PARAMETER O, PARAMETER IS NOT DEFINED O, READY 1 is a sign that the RECORD operation for a given parameter is completed and the device is ready to search object.

To continue the operation of the device, a short-term signal is CONTINUED to continue to zero level, on the leading edge of which the trigger 61 goes to the zero state. At the output of the sign of overflow of the counter 57 there is a potential drop of the signal from the zero to the unit level, which is triggered by the driver 63, which generates a short-term pulse of the unit level. END OF OBJECT SELECTION 1. This signal transfers the device for servicing messages to its initial state.

The procedure for finding the necessary parameter of the selected object in a message locked in the input register 18 in the READ mode is carried out in the same way as in the REC mode except

that it is produced under the control of the READ signal and does not check the condition for prohibiting the recording of information for each parameter of the selected object (trigger 3 by

the READ signal is not set to a single state). After selecting the required parameter, information is read from the outputs 50 of the device from the output register 45 at the address determined by the value of counter 47, the length by the value of counter 48. After reading the entire length of the recording information for this parameter of the selected object, the PARAMETER SELECT signal goes to zero

state, and when the output is READY 1, the device is ready to continue searching for the next parameter of the selected object for the subsequent READ operation to be performed. The device proceeds to search for the next parameter of the selected object after the generation of a short-term signal, CONTINUE to zero level.

If as a unit of record length

If the word is used (16 bits), for the device to work, the first bit of the address inputs of the memory block 49 must be connected to the logical zero bus, and the outputs of the counter 47 should be connected to the corresponding inputs of the block 49 with a shift of one bit in the direction of increasing their order numbers.

The device provides for the protection of information from unauthorized access by the user. When working with the specified parameters of the selected object (START signal 1) using the WRITE or READ signals, the device returns to its initial state in those situations when:

1) the user performs the operation of RECORDING information when the signal is set to PROHIBIT RECORDING OF THE PARAMETER 2) the user performs the operation of RECORDING or READING information when the signal is set, the PARAMETER is NOT DEFINED; 3) the user continues the Write or READ operation in the case when all the information on this parameter has been exhausted, i.e. when, after resetting the counter 48, the trigger 29 goes to zero.

The device has advanced functionality due to the implemented service discipline.

structured information according to the selection criterion {OBJECT (PARAMETER 1, PARAMETER 2, ..., PARAMETER F} and determining the reason for prohibiting the user from working with information on the specified parameter of the selected object (signs: PROHIBITION OF RECORDING OF THE OBJECT, PROHIBITION OF RECORDING OF THE PARAMETER, THE PARAMETER IS NOT DEFINED, OBJECT UNDEFINED). To retrieve information on some or all parameters of a given object in a known device, a time equal to

F

Tl - 2. (Tanalization + Tj sample), i 1

where Tanalization is the time taken by the device to determine the identity of the input message (object code and parameter code) among the messages of the parameter memory block by the selection criterion {OBJECT - PARAMETER};

T1 sampling is the time required to perform a write or read operation on the i-th parameter of the selected object.

In the proposed device for similar work takes time equal to

F T2 Tanalization + 2 T1 sampling. AT THIS QUESTION 1

Claims (1)

but that Ta Ti, and with an increase in the dimension F of the parameters of the object, this inequality is further enhanced. Thus, by introducing into the device a control unit, two memory units of parameter descriptors and an START trigger, a significant increase in productivity is achieved. SUMMARY OF THE INVENTION A message processing device comprising a clock pulse generator, first to sixth AND elements, an input register, a comparison node, an OR-NOT element, a first to third AND-NOT elements, a delay element, the first and second memory units; from the first to the third counters, from the first to the fifth elements of the IL AND from the first to the fourth triggers, and the output of the clock is connected to the first input of the first element And, the output of which is connected to the counting input of the first counter, the information output of which is connected it is connected to the address input of the first memory block, the output and group of outputs of which are connected respectively to the first input of the first NAND element and to the information inputs of the first group of the comparison node, the information input of the device is connected to the information inputs of the input register and the second memory block, the outputs of the input the register are connected respectively to the information inputs of the second group of the comparison node, the first input of the device mode is connected to the first input of the second element And, the output which is connected to the first input of the OR-NOT element, the output of which is connected to the installation input in 1 of the first trigger, the output of which is connected to the second input of the first AND element, the transfer output of the first counter is connected to the first inputs of the first and second OR elements, the output of the latter is connected to the first input of the third AND element, the output of which is connected to the synchronization input of the second trigger, the output of which is connected to the output of the device readiness indicator, whose second mode input connected to the first input of the second element AND NOT, to the second input of the second element And to the first input of the third OR element, the output of which is connected to the inverse input of the installation in 1 of the third trigger, the output of which is connected to the second input of the first element AND-NOT, the output the first OR element is connected to the synchronization input of the first trigger, the output of the second AND-NOT element to the first input of the fourth AND element and to the inverse recording input of the second memory block, the output of the third AND-NOT element to the inverse reading input of the second memory block and the second the input of the fourth element And, the output of which is connected to the second input of the third element And, to the counting input of the second counter and to the counting input of the decrement of the third counter, the information output of the second counter is connected to the address input of the second memory unit, the installation input to the initial state of the device is connected to the installation inputs in About the first, second and third triggers and the second and third counters, the input of the zero potential of the device is connected to the information inputs of the first and third triggers, the information input of the second the trigger is connected to the input of the unit potential of the device, characterized in that, in order to increase speed by organizing group transmission of parameters, it comprises a control unit, the output register, the seventh and eighth elements of AND, the sixth and seventh elements of OR, the first and second elements of NOT, fifth to ninth triggers, the third and fourth blocks of memory, and the output of the clock pulses connected to the synchronization input of the control unit, the first output of which is connected to the write-read inputs of the third and fourth memory blocks, the output of the third and first output of the fourth blocks the memory is connected respectively to the information inputs of the second and third counters, the output of the third counter is connected to the data input of the fourth trigger and the installation input in 1 fifth trigger, the second output of the fourth memory unit is connected to the first input of the fifth AND element, the output of which is connected to the information inputs of the fifth and sixth triggers, the inverse output of the fifth trigger is connected to the first input of the third AND element, the second input of the second AND element, and the first input of the fourth OR element, the output of which is connected to the output of the sign of the selection of the device parameter, the first input of the mode of which is connected to the second (Inverse) input of the third element AND NOT, the output of the first counter is connected to the address inputs of the third о and the fourth memory unit, the output of the second AND element is to the synchronization input of the seventh trigger, to the first input of the fifth OR element, to the first input of the sixth AND element and to the input of the first NOT element, the output of which is connected to the first input of the seventh AND element, output which is connected to the first input of the sixth OR element, the output of which is connected to the installation inputs in O of the first counter, fourth, sixth and ninth triggers of the output register, the outputs of the input register are connected respectively to the group mode inputs of the control unit , the second output of which is connected to the recording inputs of the second and third counters and the input of the second element NOT, the output of which is connected to the third input of the third element AND and the synchronization inputs of the fourth to sixth triggers, the output of the fourth trigger is connected to the output of the sign of uncertainty of the device parameter, direct output of that trigger - to the second input of the seventh AND element, the output of the sixth trigger - to the second input of the fourth OR element and the output of the sign of the prohibition of writing the device parameter, the output of the third element Y-NOT - to the delay element, the output of which is connected to the write-read input of the output register, the output of which is connected to the information output of the device, the information input of the output register is connected to the output of the second direct unit, the output of the third trigger to the second input of the fifth AND element , the transfer output of the first counter is to the synchronization input of the third trigger, the output of the first element NAND is to the information input of the eighth trigger and the first input of the eighth AND element, the output of which is connected to the synchronization input of the ninth a trigger whose output is connected to the first input of the seventh OR element, the second inputs of the OR-NOT element, the first and third OR elements, and to the information input of the seventh trigger, the output of which is connected to the second input of the fifth OR element, the first input of the control unit mode and the third input of the seventh element And, the output of the comparison node is connected to the second input of the eighth AND element and the synchronization input of the eighth trigger, the inverse output of which is connected to the second input of the seventh OR element and the output of the sign that the device message is not recorded, the output of the fifth OR element is connected to the write-read input of the input register, the output of the seventh OR element is to the second input of the second element OR, the third input of the device mode to the second input of the sixth AND element and the second input control unit mode, the third output of which is connected to the second input of the sixth OR element, the output of the sixth AND element is to the inverse input of the second trigger in О, the unit potential input and input the reset devices are connected respectively to the information input of the ninth trigger and the third input of the sixth OR element, while the control unit contains a counter, multiplexer, trigger, the first and second pulse shapers, the first and second AND-NOT elements, the AND element, and the OR element, and in the control unit, the group mode inputs of the control unit are connected to the information inputs of the multiplexer, the output of which is connected to the first inputs of the AND and OR elements, the outputs of which are connected respectively to the input of the first pulse shaper and to the first input of the first AND-NOT element, the output of which is connected to the counter counter input and the trigger synchronization input, the output of which is connected to the second input of the AND element and the first input of the second AND-NOT element, the output of which is connected to the second input of the OR element, the first input of the control unit mode is connected to the second input of the second AND-NOT element, the third input of the AND element, to the inverse input of the setting in 1 trigger and the inverse input of the setting in O of the counter, the information output of which is connected to the control input of the multiplexer and the first output of the control unit, the synchronization input of which is connected to the third input of the second NAND element, the inverse output of the counter transfer is connected to the input of the second pulse shaper and to the information input of the trigger, the second input of the control unit mode to the second input of the first element AND NOT, the fourth the input of the second AND-NOT element and the fourth input of the AND element, the outputs of the first and second pulse shapers are connected respectively to the second and third outputs of the control unit.