SU1587537A1 - Device for servicing messages - Google Patents

Abstract

The invention relates to computing and can be used in the construction of computing systems for processing large data belonging to different classes of objects. The aim of the invention is to enhance the functionality of a known device by providing the ability to work with messages of variable length and eliminate the redundancy of stored information. The device contains a clock pulse generator 1, triggers 2, ..., 5, elements AND and OR, comparison element 18, counters 19, 21 and 22, memory blocks 26-28, and an input register 24. The device provides user random access to the elements recording structured information; the ability to service variable-length messages belonging to different classes of objects. New functionality of the device increases its performance and eliminates the redundancy of information stored in the memory block. 1 il.

Description

The invention relates to computer technology and can be used to construct computer systems for processing large amounts of data belonging to different classes of objects.

The purpose of the invention is the expansion of the functionality of the device by providing the ability to work with messages of variable length and eliminate redundancy of stored information.

The drawing shows a block diagram of a device.

The device contains a clock generator 1, four triggers 2-5, four elements AND 6-9, four elements OR 10-13, element OR NOT 14, elements NOT 15-17, comparison circuit 18, counter 19, element 20 delays, counters 21 and 22, pulse shaper 23, input register 24, comparison circuit output 25, parameter memory block 26, parameter descriptor memory block 27, memory block 28, device information input 29, device information output 30, device read input 31, input 32 device entries, output: 33 device availability, output 34 parameter selection, output 35 reset the device to its initial state.

Blocks 26 and 27 of the memory can be built on the basis of electrically programmable read-only memory devices.

The code coming from the output of counter 19 to the address inputs of block 2.6 causes a 9-bit word containing 5-8th digits to appear at its output — parameter code; 1st to 4th digits - object code; The 0th digit is a sign of a ban on writing. If the 0th bit of this message is a logical unit, then writing the value of the selected parameter of this object to memory block 28 is prohibited. At the same time, the code from the output of the counter 19 also arrives at the address inputs of the parameter descriptor memory unit 27, the least significant bit being determined by the state of the output of the comparison circuit 18, depending on the state of which (0 or 1) two words are sequentially located in the memory of the block 27. The first word contains the code for the length of the parameter record (number of bytes of recording), and the second 4 is the write address of the selected parameter of this object, defined in block 26 of the parameter memory.

The delay time of the signal passing through the delay element 20 is chosen to be somewhat longer than the time from the moment the code block 27 was supplied to the address inputs, ending with the moment when the selected message was established at the outputs of this block.

Shaper 23 when a potential drop from zero to a unit level appears at its input generates a short-term pulse of a unit level at its output.

The memory unit 28 is designed to store information that can change its value over time. The information unit of writing / reading unit 28 is a single byte message, the address of which is determined by the code coming from the output of the counter 21 to the address inputs of the memory unit 28.

If the output 33 is in a single state, then this is a sign of the device’s readiness for servicing the next message or performing the next operation.

The device operates as follows.

In the initial state, after a signal of Unit Level Reset arrives at input 35 of the device, triggers 2-4 are in the zero state, trigger 5 is set to the single state, counters 19-22 are reset to zero, the output of the counter resetting counter 19 is in the single state, the signal Ready at the output of the device 33 is equal to a logical unit, the signal. The choice at the output 34 of the device is logical zero, the output 25 of the comparison element 18 is in the zero state.

The device operates in two modes: Write and Read.

In the Record mode, the information inputs of the device 29 receive a message (9 bits), the format of which corresponds to the format of messages recorded in the parameter memory 26. moat. The least significant bit of input 29 is always set to one. At the same time, a short-term signal is received at device input 32. A zero level record is used to set triggers 2 and 3 to a single state, reset trigger 5 to zero, record a message from the information inputs of the device 29 in input register 24. The least significant bit in a message is written to register 24, must always be a logical unit value. The transition of the trigger 2 to the single state allows the passage of clock pulses from the generator 1 through the element 6 to the counting input of the counter 19. When changing the counter'19 to the first information inputs of the comparison circuit 18, messages stored in the block 26 of the parameter memory are received sequentially and compared with the message located in the input register

24. If, after the counter 19 completes the complete counting cycle, no logic unit signal is generated at the output of circuit 18, this means that either in the parameter block 26 there is no message identical to the message in register 24, or in the zero bit of the message recorded in block 26 , a sign of recording prohibition has been established, which causes the appearance of the first information inputs of the logic zero signal circuit 18 at the input of the least significant bit. In this case, at the output of the sign of zeroing the counter 19, a difference is formed, the signal from zero to a single level, which causes the trigger 5 to be set to a single state and the triggers 2 and 3 are reset to zero. The passage of clock pulses from the generator 1 through the element And 6 to the counting> input of the counter 19 is terminated. The output 34 of the device remains in the zero state, and the output 33 is set to one, which is a sign that the parameter of this object in the message recorded in the register 24 is not defined in the block 26 of the parameter memory or the operation of writing the state of this parameter of this object is prohibited in the block 28 memories. Moreover, the message located in the block 26 of the parameter memory, determined by the zero state of the counter 19, is not identical among the messages received at the information inputs 29 of the device.

If the messages arriving at the information inputs of the comparison circuit 18 from the block 26 of the parameter memory and register 24 coincide, a single signal is generated at its output, which ensures the reset of triggers 2 and 3 to the zero state; blocking the passage of signals Write, ³ Reading through the OR-NOT 14 element to the input of the register register 24 and the input of setting trigger 2 to a single state; blocking the passage of the signal Recording through the element OR 1G to the inverse input of the installation of trigger 3; permission of the passage of signals. Write, Reading through the corresponding AND-NOT elements 15 and 16; setting trigger 4 to a single state · * state; writing to the counter 22 the code of the recording length of the selected parameter of this object from the block 27 of the memory of the parameter descriptors. Next, the logical unit from the output of the comparison circuit 18 is fed to the input of the least significant bit of the address input of block 27 and after a delay time causes the write address code of the selected parameter 25 of this object to appear at its outputs, after which a potential difference from zero to unity is formed at the output of delay element 20 level, which causes the record of the address-write code 30 to the counter 21 and the installation of the trigger 5 in a single state. The appearance on the outputs 33 and 34 of the device of signals Choice-1, Ready-1 is a sign that the parameter of this object is defined in the device and its state value is allowed to be written in the memory block 28. For clarity, we consider the procedure for writing to the memory unit 28 the values of the selected parameter 40 of this object with a length of 16 bits. The parameter is written in increments of 1 byte per operation. The parameter length code equal to 2 is recorded in counter 22. The first 8 bits of the parameter value are received at the information inputs 29 of the device 45, and the signal is recorded at the 32 input of the device, which is through the AND element -NOT 15 goes to the RQ5Q input of the write solution of the memory unit 28 and resets trigger 5 to the zero state (Ready-0). On the basis of the Write signal, 8 bits of the parameter value are recorded in block 28 at the address 55 determined by the contents of counter 28 and the formation of element And 8 produces a short-term zero level signal, by the difference of which from zero to unit level, the unit is subtracted from the contents of counter 22 (length unit records); adding a unit to the contents of counter 21 (record address); setting trigger 5 to a single state (Ready-1), which is a * sign of the device’s readiness to record the next batch of information in memory block 28. The second piece of information is recorded in a similar way, except that after subtracting a unit from the contents of the counter 22, a signal drop from zero to a single state is formed at its output of the zeroing indicator, which causes an appearance. at the output of the shaper 23 short-term single pulse, providing zeroing of the counter 19; resetting trigger 4, forming any output at the output of the Ready-1 signal device, and the transition of the device output 34 from a single to a zero state is a sign that the Write operation with this parameter has been completed and the device is ready for the next operation.

The procedure for searching for the required parameter of a given object, defined in the message recorded in the input register 24, in the parameter memory block 26 during the Read operation is carried out in the same way as in the Write operation, except that it is performed under the control of the Read signal and does not check the write prohibition condition (trigger 3 on the Read Level 0 signal is not set to a single state). After selecting the required parameter, information is read from the information outputs 30 of the device from the memory unit 28 at the address determined by the value of counter 21, by the length by the value of counter 22. After reading the entire length of the record for this parameter of the given signal object, the Selection goes to zero, and when setting the Ready output to a single state, the device is ready for the next Write or Read operation.

Claims (1)

Claim A device for servicing messages containing a clock generator, an input register, three counters, a comparison circuit, a memory block, four triggers, four AND elements and four OR elements, the output of the clock generator is connected to the first input of the first AND element, the output of which is connected to by the counting input of the first counter, the device reset input is connected to the installation inputs at 0 of the first and second triggers, the second and third counters, the installation input to Ί of the third trigger and the first input of the first OR element, the output of which connected to the installation input at 0 of the fourth trigger, the output of the first trigger is connected to the second input of the first AND element, the transfer output of the first counter is connected to the first outputs of the second and third OR elements, the output of which is connected to the first input of the second AND element, the output of which is connected to the input the gating of the third trigger, the output of which is the readiness output of the device, the read and write inputs of the device are connected to the first and second inputs of the third element. And accordingly, the output of which is connected to the input of the mouth new at 0 of the third trigger, the recording input of the device is connected to the first input of the fourth OR element, the output of which is connected to the installation input in 1 of the second trigger, the information input of the device is connected to the information inputs of the memory block and input register, the output of the second counter is connected to the address input of the memory block , the output of the fourth element And is connected to the subtracting input of the third counter, summing the input of the second counter and the second input of the second element And, characterized in that, in order to expand functional capabilities due to the possibility of working with messages of variable length and eliminating redundancy of stored information, an OR-NOT element, three AND-NOT elements, a delay element, a pulse shaper, a parameter memory block and a parameter descriptor memory block are inserted into it, the output of the first counter is connected to the address input of the parameter memory block and the input of the high bits of the memory block of the parameter descriptors, the high bits and the least significant bit of the output of the parameter memory block are connected to the high bits of the first information input with emy comparison and the first input of the first AND-NO element, respectively, the output of which is connected to the least significant bit of the first data input of the comparison circuit, the input register output is connected to second data input · | a comparison circuit, the output of which is connected to the first inputs of the OR-NOT element, the second and third elements AND-NOT, the second inputs of the second and fourth elements OR, the input is | beating of the fourth trigger, by the asynchronous load input of the third counter, the least significant bit of the address input of the parameter descriptors memory block and through the delay element by the asynchronous load input of the second counter 2 and the second input of the third OR element, the output of the third counter transfer is connected via the pulse generator to the reset input at 0 of the first 2 counter and the second input of the first OR element, the output of the third AND element is connected to the second input of the OR-NOT element, the output of which is connected to the input of the input register entry and input Ohm installation in 1 first. trigger, the output of the second element OR is connected to the gating inputs of the first and second triggers, the output of which is connected to the second input of the first element AND, the output of the memory block of the parameter descriptors is connected to the information inputs of the second and third counters, the output of the memory block is connected to the information output of the device, the recording and reading inputs of the device are connected to 5 by the second inputs of the second and third AND-NOT elements, the output of which is connected to the reading input of the fourth AND element, the second input of which is connected to the output of the second AND-NOT element and the recording input of the memory unit, the output of the fourth trigger is connected to the output of the device parameter selection, information the inputs of the first and second triggers are connected to the input 5 logical zero of the device, the information inputs of the third and fourth triggers are connected to the input of the logical unit of the device.