SU743030A1 - Memory - Google Patents

Description

one

This invention relates to memory devices.

A memory device is known which contains registers interconnected through recording gates, signal triggers, the number of which is equal to the number of registers, delay lines and recording resolution gates whose outputs are connected to the inputs of the subsequent register recording gates and through the delay line with a single input of the corresponding signal trigger , with the input of the corresponding register and with the zero input of the signal trigger of the previous register, the zero outputs of the signal triggers are connected to the input of the corresponding the gates of the write resolution, and the single outputs are connected to the inputs of the gates enabling the recording of the subsequent register. In this storage device, the recording of new information in each register can be carried out only after reading the information, from this register in

the subsequent register, while recording information in a register in which there is already information, is blocked. Thus, the filled register is protected from recording new information and ensures that all the registers l are sequentially filled.

The disadvantage of this device is that the information is read only from one output register, into which after reading the information from the previous register is rewritten.

The closest technical solution to the proposed is a storage device containing registers, the inputs of which are connected to the outputs of elements AND of the first group, the first inputs of which are connected to one of the input buses of the device, the elements AND

20 of the second group, one inputs of which are connected to the high registers, and outputs - to the inputs of the elements OR, the elements AND of the third and fourth groups.

the first inputs of which are connected to other input buses, control buses f 2.

A disadvantage of this device is that in case of failure of at least one register memory element, the use of a memory device becomes impossible due to the sequential passage of information through all registers.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that the device contains logical beams, informational inputs of which. connected to one of the control buses, the control inputs of the logic blocks are connected respectively to the outputs of the elements of the third and fourth groups, the second inputs of which are connected respectively-n. correspondingly with other control buses, the outputs of the logic blocks are connected respectively to the second inputs of the elements of the first and second groups

The drawing shows a block diagram of the proposed device.

The device contains the first group of AND elements that serve to enable writing, the registers of the second group of AND elements are related. to enable readout, the elements 4 OR, the first logic unit 5, which serves to control the recording, the control buses 6-6th the third group of elements 7 AND, the control bus 8, the input buses 9, the fourth group of elements 10 AND, the control bus 11, the logical block 12, which serves to control the read, input bus 13, output bus 14.

The inputs of the registers are connected to the outputs of the first inputs of which are connected to women 13. The first inputs of the elements. AND connected to the outputs of the registers jj., And the outputs from the input; am elements 4 OR. The first inputs of elements 7 and 10 And are connected, respectively, to tires 8 and 11.

The information inputs of blocks 5 and 12 are connected to the buses, which control respectively the outputs of elements 7 and 10, the second inputs of which are connected to buses 8 and 11. The outputs of blocks 5 and 12 are connected co1 directly to the second inputs of elements and

Blocks 5 and 12 are devices for sequentially allocating units in a predetermined order from a t-bit binary code.

The device works as follows.

If all registers are 2i-2 ". the memory device is OK, then on the tires n. a signal of the form 111,. E is present. When a signal arrives Writing on the first output of block 5 in accordance with the law of its operation with the arrival of a clock pulse, a signal appears that permits the recording of information in the first register 2 through the elements 1I.

Upon receipt of the second clock pulse and the signal, a single signal appears at the second output of block 5, allowing the information to be recorded in the second register 2 through elements I. And the signal allowing the recording of information can be present only on one of the outputs of block 5, providing permission to write only in one register for each call,

Similarly, when an element 1 is received at the corresponding input, the signal is read at the first output of block 12 in accordance with the principle of its operation with the arrival of a clock pulse

Signal 1 appears, which provides the information from the first register 2 to be read through elements 3 I. When the second clock pulse and signal arrive, the corresponding inputs of element 1 are received. And the single signal appears on the second output of block 12, allowing the information from the second register to be read. 2 through elements 3 And, Thus, it is provided

sequential reading of information from the registers through the elements And the signals from the outputs of the block 12.

The signals from the outputs of the elements 3, (- And through the elements 4 OR come

for weekend tires 14 of the memory device.

Claims (2)

If there are failed registers in the memory, then on the corresponding buses, instead of signal 1, a signal O is set, which ensures that the address to the failed register is skipped during both writing and reading information. In this case, an appeal is made to an operable register that immediately follows the failed ones, in accordance with the principle of operation of blocks 5 and 12. Thus, the proposed device allows blocking access to the failed registers when recording and reading information, ensuring high speed and simplicity of implementation. The invention contains a storage device containing registers, the inputs of which are connected to the outputs of the element AND of the first group, the first inputs of which are connected to one of the input buses of the device, the elements of the second group, the first inputs of which are connected to the outputs of the registers, and the outputs The elements of the third and fourth groups, the first inputs of which are connected to other input buses, control buses, are recorded in that, with the device reliability circuit, it contains logic blocks, whose information inputs connected to one of the control buses, the control inputs of the logic blocks are connected respectively to the outputs of the elements of the third and fourth groups, the second inputs of which are connected respectively to other control buses, the outputs of the logic blocks are connected respectively to the second inputs of the elements of the first and second groups . Sources of information taken into account in the examination 1. USSR author's certificate number 377887, cl. G & C 19/00, 1971. 2. USSR author's certificate number 407396, cl. G. 11 C 19/00, 1972 (prototype).