SU739516A1 - Interface - Google Patents

Description

one

The invention of computational and information-measuring equipment and can be used in the construction of information-measuring systems in which it is required to organize the exchange of information between devices operating at a speed of speed, for example, a measuring device that transmits irregularly Q data arrays , and digital computers.

Interface devices are known that contain a buffer recording unit, a decoder, a marker register, a trigger-switch, two delay elements, two valves, an OR-NOT element, a driver. V Devices simultaneously record information into one cell of the buffer storage unit and 2o read from another cell. These cells are separated by a decoder 1.

The drawbacks of such devices are a large number of connections for switching the input and output information buses of the device with memory cells, the complexity of controlling the circuit of the device and the large hardware costs of it, the heterogeneity in the structure of the device. the memory on the Mrazd shift registers and the synchronization node, the inputs of which are, respectively, the input of clock pulses and the input for reading information of the device, the outputs of the Mth digit of the shift register the memory are the information device 2 outputs.

A disadvantage of this device is its complexity.

The aim of the invention is to simplify the design of the device.

The goal is achieved by introducing an additional M-bit shift register, M-elements, and M elements of IMPLICATION into the device, with the first bits of the memory shift registers being information inputs of the device, the first bit of the additional. Shift register being an input sign of the availability of information, the inputs of the shift of the i-th bit of the Ps1mti shift registers and the additional shift register are connected to the output of the i-ro element I, the first input of which is connected to the input of clock pulses

devices, and the second input is with the direct input -i of the 1st element IMPLICATION by the output of the 1st element IMPLICATION, the inverse input of which is connected to the output of the i-bit of the additional shift register, the direct input element & The IMPLICATION of the mth bit is connected to the output of the synchronization node, the output of the M-mount of the additional shift register is the ready output of the device, the overflow output of which is connected to the output of the first IMPLICATION element.

The drawing shows a block diagram of a device comprising memory 1 consisting of shift registers 2, additional shift register 3, elements 4. IMPLICATION, AND elements 5 and synchronization node b, for example, consisting of triggers 7 and 8, information inputs 9 and outputs 10 of the device, input 11 of the indication of the presence of information of the device and output 12 of readiness, input 13 of clock pulses, input 14 of information reading. device and output 15 overflow.

The bits of the registers 2 of the same name form the memory cell 1; The shift registers 2 are informational, and the design-similar register 3 is service. H-in any discharge register 3 indicates the presence of information in this storage cell, and O indicates the absence of information. Information is promoted from left to right. Elements 4 analyze the possibility of rewriting the contents of a single memory cell into a subsequent one and control the passage of clock pulses through the elements 5. to the advance inputs of the shift registers 2. The information output synchronization node B issues a signal to shift the information in memory 1 by one step after read information from the output (rightmost) cell. ,

The device works as follows.

In the initial state, all bits of register 3 and triggers 7 and 8 are set to zero (positive logic — low voltage corresponds to O). The incoming binary code to the information inputs 9 of the device is accompanied by 1 at the input 11 of the indication of the presence of information and is always entered into the first cell to the left of the signal at the input of 13 clocks. Clock pulses are continuously fed to loop 13 and the entered code is sequentially moved through all the cells into the output cell. In this case, the entire contents of the memory is shifted in each clock cycle. As soon as the code reaches the output cell, the unit in the service area sets a high level at the output 12 of the device readiness.

and a low level at the output of the corresponding element 4, which prohibits the passage of clock pulses through the element 5 connected to it and the recording of new information into the output cell. When the next informational code is written in the next-to-last cell, a low level from the output of the last element 4 prohibits writing to this cell. The same way

Q is filled with all memory cells 1.

After reading the information, K9 the second can occur at any moment in time, from the output cell a pulse: at the input 14 of the information reading sets the trigger 8 to the one state. The first clock pulse that arrives after that cocks trigger 7 into one state, which leads to resetting the trigger and the appearance of a high level at the outputs of all

0 elements 4. The next clock pulse shifts the information in memory 1 and one step to the right and again sets trigger 7 to the zero state. The final code is the reading code to be read. Upon completion of reading this code, the procedure for shifting information in memory 1 is repeated. Low overflow signal may be low

Q at output 15 at the time of the occurrence of the unit at the input of the sign of the presence of information. The average speed of entering codes into the device should not exceed the average speed of reading, and

The number of bits in the shift registers should exclude the possibility of memory overflow 1.

Thus, the proposed device provides simultaneous input and output of information with more

0 simple compared to the prototype design.

Claims (2)

1. USSR author's certificate number 488202, cl. G About F 3/04, 1973. 2. Authors certificate of the USSR 401999, cl. G 06 F 13/02, 1971 (prototype). j Sr-HfwU.nvrt ijieii.-svvAfrbfe. , iiii .-;:; Wi-i2i G 4 / tf