SU1476482A1 - Data exchange unit - Google Patents

Abstract

The invention relates to computing and can be used in multi-machine computing systems and local data exchange networks. The aim of the invention is to increase the speed by using each of the computers (any active subscription) of any free register for the exchange at a given time. The device for information exchange contains M address and L information registers 1 and 2 of size M (M is the number of computers or active subscribers), M input blocks 3 by M + L pairs of elements And, M output blocks 4 by L pairs of elements And, 2 M elements And 5 and 2M elements And 6, M elements OR 7, M elements OR-NOT 8 and M delay elements 9. 1 Il.

Description

The invention relates to computer technology and can be used in multi-machine computing systems and in local data exchange networks.

The purpose of the invention is to increase the speed of the device by enabling each of the computers to use any register that is free for exchange at a given time.

The drawing shows a block diagram of a device.

The device for exchanging information contains M address and L information registers 1 and 2 with a capacity of M (M is the number of computers or active subscribers), M input blocks 3 by M + L pairs of AND elements, M output blocks 4 _П о L pairs of AND elements, 2M ί elements AND 5 and 6, M elements OR 7, M elements OR NOT 8 and M elements 9 delay.

All shifting device registers are made on RS-flip-flops forming a matrix; when using IK triggers, the circuit differs in that the output of the And 7 element must be connected simultaneously to the inputs j and K corresponding to the inputs R and S.

I The essence of the operation of the device is that each i-th computer can record information in any free bit of shift registers, in which the recorded information from the lowest i-ro bit in the (1 + 1) th, continuously circulates and from the senior M-th to the first, and if there is 1 in the i-th digit of the i-ro register 1, information of the i-th computer is read.

Functioning is carried out as a result of the arrival of a cyclic sequence of two clock pulses: SI 1 - recording information from a computer and reading information into a computer; SI 2 census information from the i-ro category of all registers in the (1 + 1) -th, and from the category to the first.

Since information is recorded only under the condition that all M triggers of this and address registers are in state 0, it is fundamentally impossible to simultaneously read and write information in any of the channels of the device.

The device operates as follows.

M-wasp

In the initial state, the triggers of address registers 1 and information registers are set to state 0 ”. At the outputs of the elements OR-NOT 8 formed resolving potentials. When a pulse is applied to the clock input (SI 1), it is fed through the open And 5 elements to the gate input of the 3 And block, recording information from each computer into the corresponding bits of the registers. The clock pulses (SI 1) coming from the first input, passing through elements 5 and 6, allowing or prohibiting the recording and removal of information, carry out (or do not) record information from the i-th computer to any free register or read if code 1 is written in the i-th digit of the i-ro address register, and when reading the information, the trigger (the i-ro trigger of the i-ro discharge of the i-ro address register) is reset by sending a signal from the output of the And 6 element through the delay element 9 and the OR element 7.

Claims (1)

Claim A device for exchanging information containing a matrix of M * (M + L) triggers, where M is the number of computers or active subscribers connected to the device, L is the number of bits of the transmitted information word, M pairs of elements And and M output blocks of L elements And moreover, the output K, i-ro of the matrix trigger Ci = l, (M + L), K = 1, (M-1) J is connected to the information input (K + 1), i-ro of the matrix trigger, the output M, i -ro of the matrix trigger is connected to the information input 1, i-ro of the matrix trigger, output j, of the 1st matrix trigger of the matrix [j = l, M, 1 = M, (M + L)] is connected to the first input of the Kth element And (K = l, L) j-το of the output block AND elements, the first sync input of the device is connected to the first inputs of the first and second elements AND of the jth pair of AND elements (j = l, M), the second input of the first element AND of the jth pair of AND elements is connected to the i, i-ro output of the matrix trigger (i = l, M), the output of the first element And the jth pair of elements And is connected to the second inputs of the elements And j-ro of the output block of elements And, which is, in order to increase the speed of information exchange through the use of each computer from any currently free row of the device matrix row, M elements are inserted into it OR-HE, M input blocks for (M + L) $ elements AND, M elements OR and M delay elements, and in each of the M rows of the matrix, the outputs of the first M row triggers are connected to the input of the OR-HE element of the matrix row, output jq j -ro of the element IPI-NOT (j = l, M) is connected to the second input of the second element And of the jth pair of elements And, and the output of the second element And of the jth pair of elements And is connected to a common gate input- jj j-ro of the input block AND elements, the output of the i-ro element AND of the j-th input block (i * j) is connected to the input of the i, j-ro trigger setting of the j-th row of the matrix (i = l, M + L, j = 1, M) , the output of the Kth element 1st input unit (K = 1) is connected to the first input of the 1st OR (R = 1, M, 1 = 1, M), and the output of the 1st. ^ of the OR element is connected to the installation input of the 1.1th matrix trigger (1 = 1, M), the output of the first AND element of the jth pair of AND elements (j = l, M) is connected through the jth delay element to the second input j -ro of the OR element, the second device sync input is connected to the clock inputs of all matrix triggers.