SU1295451A1 - Buffer storage - Google Patents

Abstract

The invention relates to storage devices and can be used as a buffer storage device when building exchange devices. The purpose of the invention is to expand the field of application of the device by converting data formats. The information containing the actual data and the service code is fed to inputs 2 and is written to drive 1 by addresses determined by a counter 5, the state of which is sequentially changed by the signals from input 6. When reading information, the data goes to block 3 of data shift, and the service code is in register 9, the outputs of which are connected to the synchronization unit 11 and the control inputs of the unit 3. At the same time, the data is fed to the subtractive counter 8. The device ensures matching the source and receiver data formats, while the to 3, controlled by unit 11 enables shifting data in two directions. 3 il. S cl Rig. I

Description

one

The invention relates to storage devices and can be used as a buffer storage device (RAM) when building exchange devices.

The purpose of the invention is to expand the field of application of the device by converting data formats.

FIG. 1 shows a block diagram of the device I in FIG. 2, a block diagram of the synchronization unit, FIG. 3 a block diagram of the data shift unit.

The device contains a memory block 1 with information inputs 2, a block 3. Data shift with information outputs 4, an address counter 5, control inputs b and 7, a subtraction counter 8, a register 9, an element I fflH 10, a synchronization block 11, an input 2 control and control outputs 1 3 and 1 4, Synchronization unit 11 contains triggers 15-i8, clock generator 19, driver 20, I-IGSh-HE element 21, AND elements 22-24, OR-NE element 25, HE element 26 , element 27 is delayed inputs 28-33. and outputs 34-38.

The data shift block 3 contains a shift register 39 and the elements OR 40 and. four .

The device works as follows.

Before operation, the signal at input 7 is set to zero states of the counter 5 addresses and triggers 15-17 of synchronization unit 1, and the trigger 18 of synchronization unit 11 is set to one

In the record, information words are successively entered to the information inputs 2 of the device, accompanied by a signal at the first control input b of the device, which records the information word in memory block 1 at the address generated on the address counter 5 Back leading to the signal at the first address of the memory cell ti

000

001

010

Oil

100

The bits of the information word K1 K2 KZ K4 K5 Kb K7 K8 K9 K10 K1 1 K12

1 1 1

1 o

eleven

0o

one

0o

eleven

five

0

0

50

In device control unit 6, the contents of address counter 5 are modified, i.e. A unit is added to its contents. Each information word written in memory block 1 contains four bits. The first four bits of the K) -K4 word (the controlling part of it) contain the code of the operation executed by the RAM. Bit K) contains the end of reading sign, in the last word of the data block written to the memory block 1. Bit K2 determines the blocking of the transmission to the receiver of information read from block 1 of the data memory. Short circuit bit is an identifier for the contents of bits) -4 of the information word. If 1 (, then, when performing a read operation in bits K5-KN- -4, there is a word to be output to the receiver. If, then, when performing an operation in bits K5-KN + 4, the code contains the number of bit shifts performed in the block 3 shifts in matching data formats, or a transfer delay code for the next information word receiver.5. Bit K4 determines the direction of the data shift in block 3 shifts in matching data formats.

Upon completion of writing to memory block I by the signal at input 7 of the device, address counter 5 is reset to the zero state.

The reading mode begins with the arrival of a signal at the input 12 of the control of the device. It is advisable to consider the operation of a BDU in reading mode with reference to a specific area of its use. Consider the operation of a device in read mode when it is used in an active source circuit - a passive receiver of information. Let, for example, in the recording mode in memory block 1 at consecutively increasing addresses, starting from zero, the following information array is written:

3

In the signal mode, control input 12, through the first input 28 and the OR-NOT 25 element of the synchronization block 11, records the first information word, in memory block 1 recorded at address 000, into register 9 (bits K1-K4) and subtractive counter 8 (bits K5-K12). The falling edge of the output signal of the OR-NOT 25 element is set to the one state trigger 15, which ensures that the trigger 16 is set to one state with the arrival of a positive signal differential from the generator 19 sync pulses. Setting the trigger to one state 16 causes the appearance of the signal at the output of the element 24, i.e. at output 36 of synchronization unit 11, which provides writing to the register 39 K5-K12 of the bits of the first information word of memory 1, since the value of the bit specifies for register 32 through the OR 40 and 41 elements the mode of data recording via parallel information inputs. The output signals of the register 39 are received at the information outputs 4 of the device, accompanied by a signal at the output 34 of the synchronization unit 11. The signal at the output of the AND 23 element is formed under the condition and by the delay time of half a clock of the generator 19 of clock pulses relative to the signal at output 36 of the synchronization unit 11. The signal at the output 34 of the synchronization unit 11 is an information tracking signal, in this case 01 1 1 101 1, present on the information outlets 4 devices. In this way, the first data word is output to the receiver. The unit level of the trigger signal 16 and the condition (high level of the input signal 3 of the synchronization unit 11) cause the AND-OR-HE 21 element to trigger, the output of which sets the trigger 15 and then the trigger 16 to the zero state. At the same time, a high signal level appears at the output of AND 22, since the condition (high signal at input 30 of synchronization unit 11), according to which shaper 20 generates a signal arriving at output 38 of synchronization unit 11 and modifying the contents through element OR 10 counter 5 addresses, i.e.

5 About J5 20 25 30 j Q CQ

five

514

to its contents is added one single. The output signal of the imaging unit 20, which is delayed on the delay element 27, enters the input of the WB1-HE 25 element and causes an entry in the subtractive counter 8 and the register 9 of the second information word recorded in memory block 1 at address 001. In the second word, the bit that leads to blocking the element 23, therefore, when working with this word, no tracking pulses are output to the receiver. The second word, in this case, is intended to set the time delay mode between the issuance of two consecutive words to the receiver. The binary code of the required delay is contained in the K5-K12 bits of the information word and is written into the subtractive counting bit 8.

The operation of the synchronization unit 11 in the processing of the second word is similar, however, the reset of the trigger 15 is caused by the loan signal of the subtractive counter 8 received at the input 33 of the synchronization unit 11. The output of Shaper 20 provides for modifying the contents of address 5 and, through delay element 27, the third launch of the device in read mode, in which information word 00011010 with the tracking signal on the control output 13 of the device is assigned to the receiver. The control word written at address 011 of memory block 1 provides a time delay of 128 clock cycles of the generator 19 sync pulses between the output of the second and third modified words. After issuing the third information word 11110000 to the receiver, resetting flip-flop 16 and, if conditions are present, K is a low level. The signal at input 30 of synchronization unit 11 that goes to the D-input of trigger 18, the latter is set to the zero state and at the second control output 14, a high signal level appears that indicates the end of the reading mode.

When using the device in a system with an active receiver and an active transmitter, all words recorded in memory block 1 must contain bits and in the last word K. In this case, requests for reading information must be submitted to the control input 12 of the device,

The operation of the BDU when it is used to convert data formats is similar, however, the subtractive counter 8 does not write the time delay code, but the code of the required number of bit shifts of data in the reverse shift register 39, and the direction of the shift is indicated in the K4 control word bit. So, for example, when issuing information of the AIS, SAB, ABC data sequence to the receiver, the receiver’s format exceeds the format of the transmitter and is equal to, the sequence of words written in block 1 of memory is as follows:

1 word - K1,,,

and the character code A in the K5-KN + 4 bits,

2 word -,,,

and code that provides data shift

the other inputs of the memory block, the outputs of the first group of which are connected to the information inputs of the detracting counter, the outputs of the second group of the block

5 memories are connected to the information inputs of the register, the outputs of the register group are connected to the inputs of the synchronization unit group 5 whose first output is connected to the first control input of the subtracting counter, the output of which is connected to the first input of the synchronization unit, the second output of which is connected to the second the control input of the detracting counter and to the control input of the register, the second input of the first element OR is connected to the third output of the synchronization unit, the other outputs of which are the control outputs

20 of the device, the second input of the address counter is the second control input of the device and is connected to the second input of the synchronization unit, the third input of which is the third

by N bits; 3 word -,, control (im device input, block

and character code B; 4 word K 1 1,,, and shift code for N bits; 5 word,,, and character code C; 6 word -,,, and shift code for N-1 bit; 7 word -,,, and shift code for 1 bit; 8 word -,,, K4 and shift code on N-1 bit d; 9 word -,,, and shift code per bit, etc.

Claims (1)

Invention Formula A buffer memory containing a memory block whose information inputs are the information inputs of the device, the control input of the memory block is the first control input of the device and connected to the first input of the first OR element, the output of which is connected to the first input of the address counter, outputs which are connected to the address inputs of the memory block, the outputs of the first group of which are connected to the information inputs of the detracting counter, the outputs of the second group of the block memory, are connected to the information inputs of the register, the outputs of the register group are connected to the inputs of the synchronization unit group the first output of which is connected to the first control input of the subtractive counter, the output of which is connected to the first input of the sync synchronization unit, the second output of which is connected to the second control input of the subtractive the counter and to the control input of the register, the second input of the first element OR is connected to the third output of the synchronization unit, the other outputs of which are the control outputs device, the second input of the address counter is the second control input of the device and is connected to the second input of the synchronization unit, the third input of which is the third data shift, characterized in that, in order to expand the scope of application by converting data formats, the data shift block contains the shift register, the second and third OR elements, whose outputs are connected respectively to the first and second control inputs of the shift register, information inputs the groups of which are connected to the outputs of the first group of the memory block, the outputs of the shift register are the information outputs of the device, the first and second information inputs of the shift register are connected respectively to the first and the last one of the shift register output, a third control input which is connected to the first output of the synchronization unit, the first and third inputs of second OR elements are connected to one register group outputs the second inputs of the second and third elements or connected to the outputs of the second register group. Compiled by S.Shustenko Editor I.Nikolaychuk Tehred A.Kravchuk Proofreader I.Musk Order 622/58 Circulation 590 Subscription VNISHI USSR State Committee for inventions and discoveries I13035, Moscow, Zh-35, Raushsk nab., 4/5 Manufacturing and printing company, Uzhgorod, st. Project, 4 Thebes