SU1372316A1 - Memory for graphic display - Google Patents

Abstract

The invention relates to computing technology and can be used in raster-type graphic displays. The aim of the invention is to simplify the device. The device contains 1 memory blocks arranged in three color planes 2, three shift registers 3, a decoder 4 records, three multiplexers 5, element 6, the inputs and outputs of the device. The device operates in write and read modes. 1 il.

Description

with u

with

but

The invention relates to computing and can be used in raster-type graphic displays.

The purpose of the invention is to simplify the device.

The drawing shows a block diagram of a graphical display memory for the case of three color planes.

The device contains 1 memory blocks arranged in three color planes 2, three shift registers 3, decoder 4 records, three multiplexers 5, element 6, inputs 7, addresses input 8, write resolution, mode setting input 9, inputs 10 and 11 The clock, the clock input 12, the outputs 13, the data inputs 14 and the inputs 15 of the peger registers.

The memory unit operates as follows.

In both write and read mode, address bits arrive at inputs 7, and the lower bits, which determine the memory block number in the color planes, are received, the decoder 4 inputs, and the high bits are the multiplexed cell address in memory blocks of all color planes. The reception of the two halves of the address by the memory blocks is carried out by the signals of the row address strobe (RAS) and the column address strobe (CAS) signals shifted in time (understand that the row and column refer to the internal structure of the memory blocks and for this structure).

In the read mode, the write enable signal at input 8 has a zero value, while the output of element 6 will have a zero potential, and at the outputs of the decoder 4 it will be one, corresponding to a write inhibit. Multiplexers 5 transmit signals from zero input to their outputs, i.e. single value. Multiplexers are gated with a common CAS signal on input 11 and outputs individual CAS signals for each color plane.

Information from the outputs of the memory blocks of the color planes is entered into the corresponding shift registers by the signal at input 15 and is then converted into a serial code at the outputs 13. In this case, the combination of the code of the consecutive pixels occurs.

In the recording mode, simultaneously with the RAS signal, input 10 is supplied with a high-resolution recording signal to input 8, which enables the output of the recording-enable signals at the outputs of the decoder 4. The signal to

Input 8 is applied synchronously in time with the RAS signal. At the same time, the data from the inputs 14 are recorded in the corresponding memory blocks of the color planes. If there is a single potential at input 9, which corresponds to the recording mode of only units, then the signal at input 8 will cause switching of the multiplexer inputs, in which the strobe signal will be

logically multiply with the corresponding data bit. This will lead to the fact that the signal from the output of the multiplexer will be transmitted to the input of the gating of the address of the column corresponding to the color plane only if the corresponding data bit has a single value. Otherwise, the CAS signal is not applied, the recording in the memory blocks of this plane is not made, and the information in the cells of the selected row of memory blocks is regenerated. Thus, only a few write operations are implemented.

35

Claims (1)

Invention Formula Storage device for a graphic display containing blocks memory, shift register and write decoder, whose information input is the device's address input, the address inputs of the memory blocks are the second address input of the device, the data inputs of the memory blocks are the data input of the device, the first clock inputs of the memory blocks are the first the clocking input of the device, the outputs of the memory blocks are connected to the information inputs of the corresponding shift register, the outputs of which are the data output of the device, the clocking inputs of the shift registers are the second clocking the input of the device, the control inputs of the shift registers are the control input of the device, the control input of the write decoder is input once 313723164 the recording solutions of the device, about tl i-multiplexers are connected to the input, so that, for the purpose of these devices, the second inputs of the device simplification, it contains multiplexers connected to the bus multiplexers and the element I, the output of the logical unit of the device that is connected with addressable inputs of multiplexers by multiplexers, the first input is the third clocking input of the device AND, it is the input of the task of the device, the second clocking input of the bench press, the second input of the memory memory I and I are the resolution input by the Q and the corresponding multiplexes of the device, the first inputs of the data sets.