SU525156A1

SU525156A1 - Memory matrix

Info

Publication number: SU525156A1
Application number: SU2116915A
Authority: SU
Inventors: Евгений Павлович Балашов; Михаил Степанович Куприянов; Геннадий Алексеевич Петров
Original assignee: Ленинградский Ордена Ленина Электротехнический Институт Им.В.И.Ульянова (Ленина)
Priority date: 1975-03-25
Filing date: 1975-03-25
Publication date: 1976-08-15

Description

(54) ЗАПОМИНАЮЩАЯ МАТРИЦА(54) STORAGE MATRIX

Изобретение относитс к области вычислительной техники и может -быть использовано при построении устройств хранени дискретной информации.The invention relates to the field of computer technology and can be used in the construction of discrete information storage devices.

Известны матрицы запоминающих устройетв (ЗУ), содержащие элементы пам тр объединенные по строкам и столбцам, и логические элементы.There are known memory storage matrices containing memory elements combined in rows and columns, and logic elements.

Известка матрица ЗУ, содержаща числовые линей1сИа состо щие из элементов пам ти , разр дные и адресные щины . Недостагком такой матрицы вл етс низка помехоустойчивость .Lime is a matrix of memory containing numerical lines of memory consisting of memory elements, bit and address space. The disadvantage of such a matrix is low noise immunity.

Наиболее близкой по технической сущности к данному изобретению вл етс матрица ЗУ, содержаща числовые линейки, состо щие из элементов пам ти, соединенных с адресной шиной, и основных логических элементов И, подключенных к щине считывани .посто нной информации, и разр дные щины The closest to the technical essence of this invention is the matrix of the memory, containing numerical lines consisting of memory elements connected to the address bus, and the main logic elements AND connected to the read information constant pin, and

2.2

Недостатком такой матрицы вл етс низка надежность.The disadvantage of such a matrix is low reliability.

Цель игюбретени - повышение надежност матрицы ЗУ.The purpose of izubrebeni is to increase the reliability of the memory matrix.

Это достигаетс теМ; что матрица содер жит в каждой числовой линейке дополнительные логические элементы И, каждый из которых подключен к выходу соответствующего элемента пам ти, разр дной шине и шине ечитывани оперативной информации, а основные логические элементы И подключены к соответствующим адресной и разр дной ши нам.This is achieved by teM; that the matrix contains in each numerical line additional logical elements And, each of which is connected to the output of the corresponding memory element, the bit bus and the read information bus, and the main logic elements of And are connected to the corresponding address and bit bus.

На чертеже изображена блок-схема предлагаемой матрицы.The drawing shows a block diagram of the proposed matrix.

Claims

The matrix contains in each numerical line the memory elements 1 connected to the address thickness 2, bit buses 3 and 4, additional logical elements AND B, each of which is connected to the corresponding bit memory bar, as well as to the operative information reading bar 6 and memory entry 1; The outputs of the main logic elements AND 7 are also connected to the bit buses 3 and 4, one of the inputs of each of which is connected to the address bar 2 of this numerical line, and the second to the read information bar of the constant information 8, This number is then connected to the logic element of the element 7, for example, the busbar 3 busbar, if 1, then the busbar 4 busbar. When recording information, signals are sent to the matrix from one of the address buses 2, busbars 3 and 4 and read operational information bus 6, If units are written to this bit a, then the signal arrives on the bit bus 4 through the logic element AND 5 into the memory element 1. At the same time, the memory element was in a single state, then its state does not change. If the memory element was in the zero state, its state is reversed. When writing a zero to this bit, the signal is sent to the bit bus 3, otherwise the write process O is similar to the process of write 1. To read the operational information, signals are sent to one of the address buses 2 and the real information read bus 6. If the memory element is stored 1, the logical element AND 5 is opened and the information on the bit bus 4 is displayed, if the memory element has stored O, another logical element 5 is opened and the information appears on the bit bus 3 When reading the constant information, the signals served by one and address bus 2 and readout constant information 8. If a constant number O is stored in this bit, the logical element AND 7 is opened and the information appears on the discharge bus 4. From a review of the operating modes of the matrix, it follows that the logical elements AND 5 work in the mode of bilateral conduction. For example, a MOS transistor, whose source and drain are interchangeable, can serve as such a logical element. An analysis of the operating modes of the matrix shows that the readout signal of the constant information does not affect the state of the memory elements and, therefore, its form and size are not subject to strict requirements. The invention storage matrix containing numerical lines, consisting of memory elements connected to the address bus, and the main logical elements And connected to the read bus of constant information, and bit buses, characterized in that, in order to improve reliability matrix, it contains in each numerical line additional logical elements AND, each of which is connected to the output of the corresponding memory element, the low-level bus and the operational information reading bus, and the main logical elements AND connected to the corresponding address and bit buses; Information sources taken into account during the examination: T. Aut. St. № 342222 cl. G-11C11 / 40, publ. O4.07. 1970,

2. Howe, Meili Electronics, 1971, No. 17, p. 49 (prototype) ,.