SU1532977A1 - Memory unit of "queue" type - Google Patents

Abstract

The invention relates to computing and can be used to interface computing devices with different speeds. The purpose of the invention is to simplify the memory of the "queue" type. The storage device contains a memory block 1 with write and read address inputs 2, 3, write and read information outputs 4, 5, information inputs 6, an address generation unit 7 with read control inputs 8, 9 and a record 10, 11, first and second counting triggers 12, 13, inverters of the recording unit 14, 15, the first and second elements AND-NOT 16, 17, element AND 18, trigger 19 indicating the end of the record, consisting of the element AND-OR-NOT and the inverter, MOS transistors 20 -22 write blocks, load elements 23, 24 of the write block, read permission input 25, write permission input 26 B, initial setting input 27, information input 28, output 29 indicating completion of reading, the output 30 indicating completion of the recording. Information can be written and read at arbitrary moments of time independently of each other. The conditions for performing these operations make it impossible to simultaneously write and read information from the same memory element of block 1 and ensure that at least one more cleared memory element is stored in front of the memory element, and from which at least one more memory element with information recorded in it is read. When reading an empty memory device or writing to a filled device, the read or write transients are not completed until the write or reading processes, respectively, have passed. 4 il.

Description

(/

SP

with to with vl 1

the second counting triggers 12, 13, the inverters of the recording unit 14, 15, the first and second elements AND-NOT 16, 17, element 18, trigger 19 indicating the end of recording, consisting of the element AND-OR-NOT and the inverter. MOS transistors 20-22 of the recording unit, load elements 23, 24 of the recording unit, read resolution input 25, write resolution input 26, setup input 27, information input 28, read end indication output 29, j end of write write output 30 . Information can be written and read at arbitrary moments of time independently of each other. The conditions for performing these operations make it impossible to simultaneously write and read information from the same memory element of block 1 and provide in front of the memory element into which at least one cleared memory element is written, the memory, and in front of the memory element from which reading is performed, at least one more memory element with recorded information in it. When reading an empty memory device or writing to a filled device, the read or write transients will not be completed until the write or reading processes, respectively. 4 il.

The invention relates to computing technique and can be used to interface computing devices with different speeds.

The purpose of the invention is to simplify the queue type storage device.

Figure 1 shows the structural diagram of the storage device; 2 is a diagram of a memory block; FIG. 3 is a diagram of an address generation unit; Fig. 4 shows an example of implementation of the memory element.

The memory device contains a memory block I with address inputs 2, 3 write and read, information outputs 4, 5 write and read, information inputs 6, block 7 of the formation of an address with control inputs read 8, 9 and record 10, 11, first 12 and second.13 counting triggers, inverters 14, 15 of the recording unit, the first 16 and second 17 elements AND-NOT, element 18, trigger 19 indicating the end of the recording, consisting of the element AND-OR-NOT and trigger, MOS transistors 20- 22 recording blocks, load elements 23, 24 of a recording block, read resolution input 25, recording resolution input 26 si, setup input 27, information input 28, read end indication output 29, write end indication output 30. The memory unit 1 contains memory elements 31, MOS transistors 32-35 of the write and read samples, load elements 36-39, MOS transistors 40, 41 of the write elements. Block 7 forming the address consists of elements 31

five

0

five

0

five

0

five

memory block 7, the first and second elements And 42, 43 pairs of block 7, MOS transistors 44-47 groups of block 7.

The memory elements 31 of block 1 and block 7 consist of MOSFETs 48, 49 and load elements 50, 51. The memory elements 31 of block 1 do not require an initial installation, therefore, their initial installation input 27 is connected to a common bus.

The storage device operates as follows.

Before starting, a high potential is applied to the input 27 of the initial installation (Fig. 1), as a result of which the triggers 12, 13 and all the elements 31 of the memory of block 7 will be reset to the zero state (low outputs are installed at their direct outputs, and on inverse highs), in this case, since the first memory element of block 7 has inversev inclusion, we will consider its zero state to be single. In the initial state, there are low potentials at the inputs 25-27. Then all potentials of the triggers 12 and 13 will have low potentials, 2 readings on address buses, and 3 entries also low potentials, 4, 5 discharge tires are high, low outputs 14-18 are low and, consequently, low the potentials 5 will be initially and at the outputs 29, 30. Such a state corresponds to an empty (cleared of information) memory.

The operation of the device begins with the recording of information in the first element 31.1.

the memory of block I. For this, information is exposed to input 28 (Fig. 1), and high potential is applied to input 26, as a result of which the trigger 13 is switched and its output is borrowed, i.e. at input 10 of block 7, a high potential appears. This potential is fed to the third input element Ј2.1, and to the gate of the MOSFET 44.1, which opens, while low. the potential from the output of element 31.1 of block 7 through open MOS transistors 41.1 and 46.1 will go to the inverse

the input is the output of element 31.2 of block 7, which is 15 tori 40 and 41 (figure 2). The low potential of the latter is switched to one state, and a high potential is established at its direct input - output, which will cause the appearance of the same potential at the second input of element 42.1. Since at the first input of this element there is also a high potential taken from the inal at the output of the flip-flop 13, t at the input 10 of the block 7, leads to element 42.1 (FIG. 3) and low potential at the output 20 2.1 of the first address records Closing with the MOS transistors 32 and 34 of the first memory element of block 1 (FIG. 2), the bit buses 4 appear high

trigger output 31.3, then the potentials, the output element 16

ment 42.1 will also work on address bus 2.1 with a high potential that will open MOS transistors 32.1 and 34.1 of memory element 31.1 of block 1 (figure 2). At the same time, a low potential from one of the inputs-outputs of the trigger 31.1 of block 1 will go to one of the bit buses 4 of the record, as a result of which element 16 will switch (figure 1), and the high potential from its output, having passed through element 18, will open MOS transistors 20 and 21, after which one of the inverters 14 or 15 is switched and on one of the informational inputs 6 there is a high potential that opens one of the MOS transistors 40 or 41 (Fig. 2). If the information recorded in the memory element 31.1 of the block 1. coincides with that stored in it before, then the recording process ends there, otherwise the memory element 31.1 of the block is switched, at which a low potential appears first on both bits 4 write buses, and then remains only on one of them. In any case, a sign of the end of the information recording is the coincidence of high potentials at input 6.1 and bus 4.0 or at input 6.0 and bus 4.1. After that, a trigger 19 is switched (Fig. 1), as a result of which a high potential appears at the output 30, which is a sign of the end of the transition 25 (Fig. 1) - a low potential, resulting in a flip-flop 19 at the output 30 is a low potential, which is a sign of the end of transients in the second

30 phase recording. Thus, the storage device turned out to be in a state similar to the initial one, with the only thing that in its first memory element 31 of block 1 is recorded information

35 element 31.2 of memory of block 7 and trigger 13 are in a single state

The following supply of high potential to input 26 will cause the appearance of potential at the output of the transfer

40 trigger 13, i.e. input 7 is block 7. This potential will open the MOS-transistor 44.2 (FIG. 3) and the low potential from the inverse output of the element 31.2 of block 7 through open MOS-trans.

45 tori 44.2 and 46.2 go to the inverse input - output element 31.3 block 7, which will cause the latter to switch to one state, which calls for the operation of element 42.2,

50 on the address bus 2.2 records for Vits high potential. Next, the information is recorded in the second element 31.2 of the memory of block 1, and the transition process in the device is completed

55 by the appearance of a high potential at exit 30 (FIG. 1).

Thereafter, the low potential is re-established at the input 26 and the device again returns to the

recording processes.

After the appearance of a high potential at the output 30, the low potential is again restored at the input 26, as a result of which low potentials appear at the output of the element 18 and the output of the trigger 13. A low potential at the output of the element, 18 closes the MOS transistors 20 and 21, high inputs appear at the inputs of inverters 14 and 15, and low potentials appear at their outputs, which close the input MOS transistor at the output of a flip-flop 13, t, e, at input 10 of block 7, leads to the switching of the element 42.1 (FIG. 3) and the appearance of a low potential at the output 2.1 of the first write address. They are closed with MOS transistors 32 and 34 of the first memory element of block 1 (FIG. 2), and high-voltage bus 4 appears

potentials at the output of element 16

(Fig. 1) low potential, whereby trigger 19 is switched and low potential appears at output 30, which is a sign of the end of transients in the second

write phase. Thus, the storage device was in a state similar to the original one, with the only difference that in its first memory element 31.1 of block 1 information was recorded,

memory element 31.2 of block 7 and trigger 13 are in a single state.

The next high potential input to input 26 will cause a high potential at the transfer output.

trigger 13, i.e. at input 11 of block 7. This potential will open the MOSFET 44.2 (FIG. 3) and the low potential from the inverse output of element 31.2 of block 7 through open MOS transistors 44.2 and 46.2 go to the inverse input - output of element 31.3 of block - 7, which will cause switching the latter to one state, which will trigger item 42.2, and

On the address bus 2.2 records for Vits high potential. Next, the information is recorded in the second memory element 31.2 of block 1, and the transient process in the device is completed

the appearance of a high potential at the output 30 (figure 1).

After that, the low potential is re-established at the input 26 and the device returns to the same state as the original, but now the information is already recorded in the first and second memory of unit 1. in one state will be. The triggers are 31.1, 32.2, and 32.3 blocks 7, and the trigger 13 will again be in the zero state. A sign of the completion of the device return process to it. The condition is the appearance of a low potential at output 30.

To read the information on the input 25, a high potential is given, as a result of which the trigger 12 is switched and on its output loan, i.e. at the input 8 of the block 7, a high potential appears, which opens the MOS transistor 45.p, and a low potential from the direct output of the element 31.p of the block 7 through the open MOS transistors 45.p and 47.p arrives at the inverse input - output of the element 31.1 of block 7, causing switching of the trigger 31.1 of block 7. At the direct output of this trigger a high potential appears, which leads to the operation of the element 43, and the appearance of a high potential on the Address bus 3.1. reading. The switching condition of the trigger 31.1 of the block 7 is the single state of the trigger 31.2 of the block 7, the high potential t of the direct output of which opens, the MOS transistor 47, n, i.e. it is necessary that the Information be pre-recorded in memory element 31.1 block 1 (no record can be read). The high potential at the address reading 3.1 is opened by the MOS transistors 33.1 and 35.1 (FIG. 2), the low potential from one of the outputs of the memory element 31 „1 of the block 1 enters the corresponding bus 5.0 or 5.1, with the result that 17 (FIG. 1), i.e. at the output 29 of the device, a high potential appears that. is a sign of the end of the transients of the first reading phase.

After that, a low potential is restored at the input 25, as a result of which a low potential appears at the output of the loan of the trigger 12, which, having entered the input 8 of the block 7, leads to the appearance of a high potential at the output of the element 43. p. e. on the reading address bus 3.1, because of which MOS transistors 33.1 and 35.1 (Fig. 2) are closed and high potentials are restored on both discharge buses 5, causing a low potential at the output of the element 17 (Fig. 1), those. at the output 29 of the device, the latter is a sign of the end of the transients of the second reading phase. Upon completion of this phase, the device is in a state similar to the initial one, with the first memory element 31.1 of block 1 cleared, and the trigger 12 is in the unit state.

The next supply of high potential to the input 25 will cause a high potential at the transfer output of the trigger 12, i.e. at the input 9 of block 7, the MOS transistor 45.1 will open (Fig. 3) .and if the transistor 47.1 is open, which corresponds to the unit state of the element 31.3 of the block 7, then the low potential from the output of the element 31.1 of the block 7 goes to the direct input - the output of the element 31.2 - block 7 and translates this element into the zero state, which will cause reading from the memory element 31.2 of block 1, which will be completed by the appearance of a high potential at the output 29 of the device.

Thereafter, a low potential is again restored at the input 25 and the device enters a state similar to the initial one, which is completed by the appearance of a low potential at the output 29.

Claims (1)

Invention Formula A storage device such as a queue containing a memory block consisting of n memory elements, where n is the information capacity of the device, the first and second AND-NOT elements, the inputs of the first AND-NE element are connected to the direct and inverse bit write buses of the block the memory, the inputs of the second AND element are NOT connected to the direct and. inverse bit, read memory bus, element AND-OR-NOT, inverter, the output of which is the output of the sign of the end of the recording device, the input of the inverter is connected to the output of the element AND-OR-NOT, the first and second inputs of the first group of which are connected respectively with the outputs of the inverter and the first element NAND, the first and second inputs of the second group of the element AND-OR-NOT are connected respectively to the direct bit write bus of the memory block and the first information input of the memory block, the first and second inputs of the third group of the AND element -OR NO connected to the inverse bit memory write bus and the second information input of the memory block, the AND element, the first input of which is connected to the output of the first AND-NOT element, the second input of which is the recording enable input of the device, the output of the second AND element NOT is the output of the sign of the end of the reading of the device, a write block consisting of the first, second and third MOS transistors of the first and second load elements, the first and second inverters, the outputs of the first and second inverters of the recording unit enes to data inputs of the memory block, the inputs of the first inverters and second recording unit are connected to first terminals of the first and second load elements respectively recording block, secondary 25 and the group address generating unit, The first and second load cell terminals are connected to the device power bus, the sources of the first and second MOS transistors of the recording unit are connected to the inputs of the first and second inverters of the recording unit, respectively, the gates of the first and second inverters of the recording unit, respectively, the gates of the first and second MOPs. -transistors are connected to the output of the element AND, the sources of the first and second MOS transistors are connected respectively to the drain and the gate of the third MOS transistor of the recording unit, the gate of which is informational the device input, the source of the third MOS transistor is connected to the zero potential bus of the device, the first and second trigger, the synchronization input of the first trigger is the read enable input of the device, the synchronization input of the second trigger is connected to the second input of the AND element and is the write enable input of the device-. The inputs, the initial setup of the triggers are combined and are the corresponding input of the device, the address generation unit consisting of n memory elements, the initial installation inputs of which are connected to the inputs of the initial installation of the device, n groups of MOS transistors, n pairs of I elements, the outputs of the first elements And the 1st the pairs (, l,.,. n) are connected to the corresponding write inputs of the memory block, the sources of the first and second MOS transistors of the i-th group of the address formation unit are connected to the drains of the third and fourth MOS transistors of the i-th group, respectively address generation, inverse and direct inputs-outputs of the 1st memory element of the address generation unit (, p) are connected to the drains of the first and second MOS transistors, respectively, of the 1st group of the address generation unit, sources of the third and fourth MOS transistors of the 1st group block formation hell , with the gates of the third and fourth MOS transistors (G2) -th group of the address generation unit and with the first inputs of the second and first elements K, respectively (1-1), and the group and the second inputs of the first and second elements AND, respectively (i-2 a) the third inputs of the first and second elements And the odd pairs of the address generation unit are connected respectively to the loan outputs of the second and first triggers, the transfer outputs of which are connected to the third inputs of the first and second elements And respectively the even pairs of the address generation unit, so that In order to simplify the device, the inverse and direct inputs / outputs of the first memory element of the address generation unit are connected to the drains of the second and first MOS transistors, respectively, of the first group, sources of the fourth and third MOS transistors, respectively, of the p-groups, gates of the fourth and third MOS- transistors respectively (p-1) -th group the address generation unit with the first inputs of the first and second elements AND, respectively, the nth and second inputs of the second and first elements AND, respectively (n-1) -th pair of the block the formation of addresses, the outputs of the second elements And the n-th pair of the block of formation of addresses (, n-1) are connected to the (1 + 1) -th input of the memory Ti, the output of the second element And the n-th pair of the address-shaping unit is connected to the first reading input of the memory unit. 1532977 one € .0 fflui, 2 37 U o 6L 1l 31 5V7 gI 45 one Vn P I U I Fpg four