SU1725237A1 - Device for selecting object attributes - Google Patents

Abstract

The invention relates to automation and computing, in particular, to devices for selecting signs of objects, and can be used in pattern recognition during various technological operations. The purpose of the invention is to expand the scope by providing a procedure for inputting non-deterministic recognizable objects in real time - by introducing a feature update block, a query block, three AND elements, two OR elements, three groups of OR elements, and a trigger. 5 il.

Description

The invention relates to the field of automation and computer technology, in particular, to devices for selecting signs of objects, and can be used in pattern recognition during various technological operations.

The purpose of the invention is to expand the scope of application by providing a procedure for inputting signs of non-deterministic recognizable objects in real time.

FIG. 1 is a block diagram of the device; in fig. 2 - feature update unit; in fig. 3 - block issuing requests; in fig. 4 - address selector; in fig. 5 - the third memory block ..

The device (Fig. 1) contains the first 1, second 2 and third 3 memory blocks, the reversible counter 4, the decoder 5, the first element AND 6, the inverter 7, the register 8, the adder 9, the first element OR 10, the first 11, the second 12 , the third 13 and the fourth 14 delay elements, the address selector 15, the feature update block 16, the query issuing block 17, the second 18, the third 19 and the fourth 20 elements And, the second 21, the third 22, the fourth 23, the fifth 24 and the sixth 25 elements OR, trigger 26, first control input 27, second control input 28, third control input 29, group of information inputs 30, information 31 input; synchronization input 32; clock input 33; first information output 34; second information output 35.

The feature update unit (FIG. 2) contains the first 36 and second 37 elements And the first group of elements 38, the shift register 39, the counter 40, the element 41, the decoder 42, the trigger 43, the first 44, the second 45 and the third 46 delay elements , information input 47, control input 48, clock input 49, synchronization input 49a, first group of information outputs 50, second group of information outputs 51.

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The request block (Fig. 3) contains the first 52 and second 53 elements And, the first 54 and second 55 triggers, shift register 56, counter 57, group And elements 58, delay element 59, information input 60, synchronizing input 61, controlling input 62, clock input 63, information output 64, control output 65.

The address selector (Fig. 4) contains the first 66, the second 67, the third 68, the fourth 69, the fifth 70 outputs of block 71, the sixth 72 And element, the first trigger 73, the second trigger 74, the third trigger 75, the first 76, the second 77, the third 78, the fourth 79, the fifth 80 and the sixth 81 elements OR, the first 82, the second 83 and the third 84 delay elements, the control input 85, the group of information inputs 86, the first output 87, the second output 88, the first group of outputs 89, the second group of exits 90.

The third memory block (Fig. 5) contains the first 91, the second 92 and the third 93 registers, the first 94, the second 95, the third 96, the fourth 97, the fifth 98 and the sixth 99 group of elements AND, the group of elements OR 100, information input 101 , a group of control inputs 102, a synchronization input 103, an output 104.

The first 1 memory block is made in the form of a persistent storage device, in fixed cells of which the base addresses are stored, from which the signs start at the respective recognition objects.

The second memory block is made according to the address structure.

The device works as follows.

The sequence of features characterizing each of the specified recognition objects is pre-recorded in memory block 2 (Fig. 1).

The identification of any of the objects leads to the appearance of an identification signal at one of the bits of the group of inputs 30 (Fig. 1).

Let us assume that such a signal is applied to the first bit of the group of inputs 30 (Fig. 1), from where it arrives at the inputs of the And 66 and 67 elements (Fig. 4). However, only the AND 67 element will be open at the second input, since it is connected to the direct output of the trigger 73, which is in the initial (zero) state, and the AND 66 element will be locked with a low potential from the inverse output of the same trigger.

Passing the element AND 67 (Fig. 4), the identification pulse through the elements OR 77 and 78 is fed to the R-inputs of the flip-flops 74 and 75, confirming their zero state, through

the OR 80 element — to the output of the first bit of the first group of outputs 89, and also through the delay element 82 — to the S input of the flip-flop 73, set it to unit state 5. In addition, the same impulse goes to the output of the first bit of the second group of outputs 90 of the selector directly and through the element OR 81 to output 88.

The identification pulse from the first time 10 row of group 89 (Fig. 4) is fed to the inputs of the group of elements I 94-96 (Fig. 5) and the synchronizing inputs of registers 91-93. However, since the groups of elements 94-96 are closed at the potential input by low

15 potential from the inverse outputs of the flip-flops 73-75, the arrival of the sync pulse for the first bit of group 102 has no effect on the state of the registers 91-93.

0 After the delay of the identification pulse on the element 82 (Fig. 4) for the time determined by the response time of the registers 91-93 (Fig. 5), it enters the S input of the trigger 73, sets it to

5, a single state in which the element AND 66 opens with a high potential and the element 67 67 closes with a low potential. In addition, a high potential from the direct output of the trigger 73 is output to the second

0 bit group 89, where it enters the corresponding inputs of the elements And 94 and 97 of block 3 and opens them on one of the inputs. In addition, the same pulse from the output 88 (Fig, 4) goes to the synchronizing

5 the input of the reversible counter 4 and the inputs of the corresponding elements AND 97-99 (FIG. 5), connecting the outputs of the register 91 through the OR element 100 and the output 104 to the information inputs of the reversing counter 4. However, since in the initial state all the registers 91- 93 were reset, then zero information is entered into the reversing counter 4 via information buses. From the first bit of the second group of outputs 90

5 (Fig. 4) of the address selector, the same pulse through the OR element 21 (Fig. 1) is fed to the input of the fixed cell of block 1, where the base address of the array of features characterizing the object of identification is written.

0 This address from the output of block 1 via information buses is entered with a paraphase code into register 8 by the sync signal from the output of delay element 11. The last from the output of the element 11 delay, pass the element IL AND

5 to 10 is fed to the input of the second delay element 12, where it is delayed by the time the code is set in register 8.

From the output of register 8 and reverse

counter 4, in which at this point in time there are only zeros, their contents arrive

to the input of the adder 9, where the sync signal from the output of the delay element 12 forms the final result that arrives at the address input of the memory block 2, the read input of which receives a signal from the output of the delay element 13, which delays the clock pulse during the transients in the adder.

As a result, the output 34 (Fig. Of the device outputs the contents of the corresponding memory cell of the memory block as the code of the corresponding attribute, and the read pulse itself goes to the summing input of the reversible counter 4 and increases its contents by one. In addition, the same pulse after a delay at element 14, for the time of reading the sign, it arrives at the waste input of the adder 9 and sets it to the initial state.

If the next sign of the same object is obtained, then an identification impulse is sent again to the first discharge of the group of inputs 30 (Fig. 1). However, now this impulse will pass through the AND 66 element open on the second input (FIG. 4) and the OR 79 element to the selector output 87, from where the OR 10 element enters the input of the delay element 12 and then to the clock input of the adder 9, in which the contents of the base address will be added to the contents of the reversible counter, increasing by one the next read address, etc.

The described process of issuing information about the features of the object will continue in a similar way until the identification pulses for the first discharge of the group of inputs 30 (Fig. 1). If it is necessary to return to the previous sign, the Return key (not shown) is pressed, as a result of which a pulse appears at the input 23, which arrives at the input of the element And 6, to another input which receives a high potential from the output of the inverter 7 connected to the output of the decoder 5. The decoder 5 outputs a high potential only if the content of the reversible counter 4 is zero. Since we consider the case of a return to a previously previous sign, the number of viewed signs is already recorded in the up-down counter 4. As a result, the potential will be low at the output of the decoder, and high at the output of the inverter. At. This impulse from input 23, passed through the element AND 6, goes both to the subtracting input of the reversible counter 4, reducing its content by one, and through the elements OR 10 and delay 12 (Fig. 1) to the synchronizing input of the adder, ensuring the formation of the address at the input memory block.

A pulse from the output of the delay element 13 (Fig. 1} at the address determined by the code in the adder 9 reads the contents of the corresponding cell of memory block 2, and then the pulse from the output of the delay element 14 delays the adder to its initial state. Pressing the Return key again will cause an analysis of the signs of objects in the reverse paging until the contents of the reversible counter 4 equals 0. This moment will be fixed by the decoder 5 by issuing a high potential, which after inverting by inverter 7 will block lement and 6 for the second input.

The need to classify another

0 of the object will result in the appearance of a signal at another input of the selector 15 (Fig. 1), for example, at the second discharge of a group of inputs 30. This pulse will pass through the element I 69 open in its initial state (Fig. 4) and through

5, the element OR 80 will go down for the first bit of the first group of outputs 89 of the selector, from where it will go to the clock inputs of elements 94-96. Since only the elements 94 and 97 will be opened by the potential of the trigger 73 (Fig. 4), the pulse from the first bit of the group 102 will overwrite the contents of the reversing counter 4 in the register 91, and the pulse from the output of the delay element 83 and the OR element 81 (output 88) register contents 92

5 through the elements OR 98 and 100 will be rewritten into the reversible counter 4. When the fact is recorded that there are no signs in the memory of the device, characterizing the object of identification, to the input 29 of the device (Fig. 1)

0 is signaled. This signal is fed to the input of the element And 52 (Fig. 3), to the other input of which the resolving potential is fed from the inverse output of the trigger 26, which is in the zero state. Signal

5, the feature request passes through the AND element 52 to the S input of the trigger 54, setting it to one. At the same time, elements of both the group 58 and the code of the address of the memory cell from the output of the adder 9 through

0 input 60 of the block 17 is fed to the information input of the register 56 shift. The same request pulse is delayed by element 59 (Fig. 3) for the time that the output of the adder 9 is connected to the input of register 56 and arrives at

5 synchronous register 56, writing in it the address code.

At the same time, the same impulse arrives at the S input of the trigger 55, converting it to a single state. High potential trigger 55 switches register 56 into

the shift mode and opens the element AND 53, to the other input of which the shift pulses begin to arrive, which carry out serially serial output of the code of the address of the characteristic of block 2 to the output 64 (Fig. 3). This procedure for issuing an address code is due to the fact that the communication channel with a remote database operates only in sequential code.

The number of shift pulses is fixed by the counter 57, and as soon as the code from register 56 is fully outputted at output 64, the output of the overflow of counter 57 results in a pulse that will return the triggers 54 and 56 to the initial state.

Upon availability of the requested data, input 24 receives a ready signal, which sets trigger 26 into one state, in which it closes element 18 of low potential from the inverse output, and also blocks input 17 of block 17 through input 61. High potential from The main output of the trigger 26 through the input 48 (Fig. 2) is fed to the inputs of the And 36 and 37 elements. With a delay of the response time of the trigger 26, the serial code from the communication channel is fed to the input of the block 47 of the block 16.

The message structure has the form: an identification code and a content code.

At the same time, the synchronous input of the register 39 from the output of the And 37 element receives clock pulses that write the code to the register 39. After recording the next bit into the register 39, the pulse from the output of the And 37 element is delayed by the delay element 44 at the recording time in the register 39 and fed to the S input of the trigger 43, setting it to the unit state in which it switches the register 39 to the shift mode with a high potential and opens the element AND 41 through which the next shift pulse from the input 49a enters the input of the shift of the register 39.

After the shift of the code in register 39 with the same pulse delayed by the shift time by element 45, the trigger 43 returns to the initial state and again switches the register 39 to the write mode.

A counter 40 (FIG. 2) counts the number of shift pulses, and as soon as all the bits are received by register 39, the overflow output of counter 40 causes an impulse to appear, through element 46, a delay pulse for transient time, and a decoder 42 enters the inputs of the group of elements And 38 and the last bit of the group of outputs 51 (Fig. 2).

The decoder 42 decrypts the code of the sign and opens one of the elements AND

group 38, through which the pulse from the output of the delay element 46 is supplied to one of the outputs of the group 51 (Fig. 2), respectively. From where this pulse passes through the corresponding element OR 21-23 and further to the corresponding read input of memory 1. In parallel with this, the pulse from the second output of the block 16 resets the reversible counter 4,

0 simultaneously, a pulse passes through the OR element 24 to the input of the delay element, where it is delayed by the time it takes to read the address code from block 1 and then goes to the clock input of register 8, skidded

5 in it the code from the output of block 1.

In addition, the same pulse through the elements OR 10 and the delay 12 is fed to the clock input of the adder 9, blocking in it the code only from the output of the register 8,

0 because the reversible counter is reset. After a delay by element 13 for the time of operation of the adder, a pulse from its output passes through element I 19 to the input of the recording control unit 2, recording the content part of the sign in the memory cell with the address specified in adder 9.

The same pulse resets the trigger 2.6 and through the OR element 22, the delay element 14 and the AND element 20 passes to the reset input of the adder 9, setting it to the initial state.

Claims (1)

Thus, the introduction of new blocks and links made it possible to introduce features of non-deterministic recognizable objects and expand the field of application of the device. Claims device for feature selection 0 objects containing an address selector whose information inputs are a group of information inputs of the device, a first memory block whose output is connected to the information input of the first register, the output of which is connected to the first information input of the adder, the second information input of which is connected to the output of the reversible counter and the output is connected to the address input of the second memory block, the output of which is the first information output of the device, the first OR element, the first input of which is connected to the blue the first input of the first register is connected to the output of the first delay element, the second input is connected to the first output of the address selector, and the output is connected to the input of the second delay element whose output is connected to the clock input of the adder and the input of the third delay element with the output of the decoder, and the output is connected to one of the inputs of the first element And, the other input of which is the first control input of the device, the output of the first element And is connected to the subtractive input reverse a clock counter whose input is connected to the second output of the address selector, and the output is connected to the input of the decoder and to the information input of the third memory block, the group of control inputs of which is connected to the output group of the address selector, the clock input is connected to the third output of the address selector, the synchronizing the input is connected to the second output of the address selector, and the output is connected to the information input of the reversible counter, and a fourth delay element, characterized in that, in order to expand the area n name, by providing the ability to enter signs of non-deterministic recognizable objects in real time, the second, third, fourth, fifth and sixth OR elements are entered, the signs update block, the second, third and fourth And elements, the trigger, the request block, the first inputs of the second of the third and fourth elements OR are connected bitwise to the second group of information outputs of the block, updating the signs, the first group of information outputs of which is connected to the group of information inputs of the second b The memory, informational, synchronizing and clocking inputs of the tracer update unit are the device inputs of the same name, the second inputs of the second, third and fourth OR elements are connected bitwise to the second group of the address selector outputs, the outputs of the second, third and fourth elements OR are connected to the corresponding the read inputs of the first memory block, the first input of the n the OR element is combined with the installation input of the reversible counter and connected to the control output of the feature update unit, the second input of the fifth OR element is connected to the second output of the address selector, and the output to the input of the first delay element, the first and second inputs of the sixth OR element are combined respectively with the inputs Write, Read the second memory block and are connected to the outputs of the second and third elements And, respectively, the first inputs of which are combined and connected to the output of the third delay element, and the second ones are combined with the control inputs address selector. and the tracer update unit and are connected respectively to the inverse and direct outputs of the trigger, whose S input is the second control input of the device, and the R input is connected to the output of the third element AND, the output of the sixth element OR is connected to the input of the fourth element delay, the output of which is connected to the second input of the fourth element And, the first input of which connected to the control output of the request unit, and the output is connected to the clock input of the adder, the information input of the request unit is connected to the output of the adder, the clock input is the clock input of the device, the control input is the third control input of the device, the clock input is connected to inverse trigger output, informational the output is the second information output of the device. zi LCZSZLl and FIG A  one 5