SU1640713A1 - Data selector - Google Patents

Abstract

This invention relates to computing and instrumentation technology. The purpose of the invention is to expand the functionality by searching for information both on external media and in the memory of direct sampling. The device contains a mode selection unit 1, an array search unit 2 in the array memory, an array transfer control unit to a buffer memory, an array transfer unit 4, an array search unit on external media, an array memory unit 6, block 7 buffer memory. 8 il.

Description

WITH

with

about

4 Oh x |

WITH

 This invention relates to computing and instrumentation technology.

The purpose of the invention is to expand the functionality by searching for information both on external media and in the memory of direct sampling.

FIG. 1 shows a block diagram of the device; in fig. 2 is a diagram of a mode selection block; in fig. 3 is a diagram of an array search block in the array memory; in fig. 4 is a diagram of a control unit for transferring from the array memory to the buffer memory; in fig. 5 is a block diagram of the transmission array; in fig. 6 is a diagram of an array search block on an external medium; in fig. 7 - the structure of the desired array, located on an external carrier; in fig. 8 - structure of the library of arrays located in the memory block of the array.

The device contains (Fig. 1) the mode selection block 1, the array search block 2 in the array memory, the transfer control block 3 from the array memory to the buffer memory, the array transfer block 4, the array search block 5 on external media, the memory block b These arrays, buffer storage unit 7, device control inputs 8, device address inputs 9, device data inputs 10, array inputs 11, synchronous input 12, output 13 of the array nondetecting attribute, 14 - 65 - block inputs and outputs.

The mode selection block 1 (Fig. 2) contains the first 66 decoder, the first element And 67, the second element And 68, the first trigger 69, the third element And 70, the fourth element And 71, the first element OR 72, the second element OR 73, the second trigger 74, the fifth element AND 75, the generator 76 pulses, the third element OR 77, the fourth element OR 78, the third trigger 79, the fifth element OR 80, the fourth trigger 81, the sixth element AND 82, the seventh element AND 83, the first switch 84, the fifth trigger 85, the eighth element E86, the second switch 87, the sixth trigger 88, the ninth element And 89, the tenth element And 90.

Block 2 of the array search in the array memory (Fig. 3) contains the first element AND 91, the first delay element 92, the second element AND 93, the first element NOT 94, the first group of elements And 95, the first counter 96 pulses, the second group of elements And 97 , the first group of elements OR 98, the first decoder 99, the first comparison node 100, the first trigger 101, the third group of elements AND 102, the first register 103, the second element NOT 104.

The unit 3 for controlling the transfer from the array memory to the buffer memory (FIG. 4) contains; The first group of elements And 105, outputs 106, the first decoder 107, the second group of elements And 108, the first register 109, the second register 110, the first adder 111, the second adder 112, the first element

And 113, the first delay element 114, the third group of elements AND 115, the first pulse counter 116, the second element IL 117, the first element OR 118, the first comparison node 119, the fourth group of elements

0 and 120.

Block 4 of the array transfer (Fig. 5) contains the first element OR 121, the first group of elements AND 122, the first counter 123 pulses, the first decoder 124, the first element AND 125, the first register 126, the second group of elements AND 127, the third group of elements AND 128, the first group of OR. 129 elements, the first delay element 130, the second element AND 131, the second element

0 OR 132.

The array search unit 5 on the external medium (Fig. 6) contains the array allocation unit 133 on the external medium, the shift register 134, the signal generating unit 135

5 offset, outputs 136-142 of array allocation node 133, inputs 143-149 and outputs 150-153 of offset shaping node 135, inputs 154-156 of shift register 134, inputs 157-159, outputs 160-164 and lines 165, 166, 167.

0 The mode selection block 1 sets four device operation modes: searching for an array only on external media; array search only in block 6 of the permanent memory; search for an array on external media with continued search in the fixed memory block; array search in block 6 of persistent memory with continued search on external media. In the initial position when the signal is received. Resetting from the control bus 8

0 via line 165 The reset to control input 17 of mode selector block 1, trigger 85 and trigger 88, are set to one, and triggers 74, 79, 69, 81 to zero.

If you need to search

5 of the array only in block 6, which can be either permanent or random-access memory, then for this, using the switch 87, the trigger 88 is transferred to the zero state, thereby keeping the AND 89 element in

0 closed state, not allowing the signal to pass. Starting to read information from external media to output 19 of mode selector 1 and preparing for opening element 90. When a 5 signal chip was received from the bus 9 address at address 15 of mode selector 1 and control The recording signal from the control bus 8 at the input 16 of the mode selector 1 opens the element And 67, which leads to the trigger trigger 81, and through the element

OR 77 to flip the trigger 74. The signal from the direct output of the trigger 74 opens the element AND 75 through which the clock pulses produced by the generator 76 to the output 20 of the mode selection unit 1 begin to pass. If the required array in block b is not found, then the signal applied to input 18 of block 1 through AND 90 closes the AND 75 element and enters the input of the OR 80 element. At output 13 of Block 1, the Interrupt signal appears. In addition, the signal at input 18 of block 1 through the OR element 73 sets the trigger 74 to the zero state, and through the element And 71, the element OR 72 sets the trigger 79 to the single position.

If it is necessary to search the array only on external media, then using the first switch 84, the trigger 85 is set to the zero position, thereby preparing the opening element 86 and closing the element 75. If there is a signal at address input 15 of block 1 and a signal the control input 16 through the decoder 66 opens the element And 68. This leads to the flip-flop of the trigger 69, as well as through the OR element 72 to the flip-flop of the trigger 79. The signal from the direct output of the trigger 79 opens the element 89 is Start signal for reading information from external media.

If the required array is not found on the external media and the information from the external media is read completely, then a signal appears at the input 21 of block 1, which through the element 86 and the element OR 80 generates a signal Interrupt to the output 13 of block 1. At the same time this signal through the element And 83, the element OR 77 translates the trigger 74 into a single position, and through the element OR 78 translates the trigger 79 into the zero position.

If it is necessary to specify the search mode of the array on the external media with the search continued in block 6, for this, through the decoder 66, the element 68 and the trigger 69 are set to one state, and through the element OR 72 the trigger 79 is set to one. flip-flop 79 opens element 89 and at the output 19 of block 1 a start signal appears for reading information from external media. If the required array is not found on the external media, then, by the signal to read information from the external media at the input 21 of the mode selection unit 1, through the element AND 83, the element OR 77 trigger 74 is set to the single position, and the trigger 79 through element OR

78 returns to the zero state. This leads to the closure of the element And 89 and the opening of the element And 75. At the output 20 of block 1, the sync pulses appear. If the required array is not found in block 6, then the signal at input 18 of block 1 through element AND 70 is fed to the input of element OR 80. Output signal 13 is removed from output 13 of block 1 (sign of undetectable array).

0 For setting the fourth mode, through the decoder 66, the element And 67 flips the trigger 81, and through the element OR 77 flips the trigger 74. This leads to the opening of the element And 75 and the appearance of a sync pulse at the output 20 of block 1. If the array in block 6 does not is found, then the signal at the input 18 of the mode selection unit 1 through the element AND 71, the element OR 72 sets the trigger 79 to the one state, and through

0, the OR element 73 returns the trigger 74 to the zero state. This results in closing element 75 and opening element 89 from the output 19 of the mode selector 1, the start signal is read to read information from the external medium. If the array is not found on the external media, the input 21 of the mode selector 1 through the element AND82 passes to the element OR 80. From output 13 of block 1, a signal is canceled.

Block 2 works as follows. On the Reset signal coming from the control bus 8 via the line 165 Reset to the control input 29 of block 2 trigger 101

5 is set to one, and the pulse counter 96 and the register 103 are zeroed. If there is a corresponding address at input 26 and a signal Recording from line 166 Recording at control input 25 of block 2, first, from the bus 10 of data, through a group of inputs 27, a group of elements AND 95 in the pulse counter 96 records the starting address of the library (Anachbibl) and then through the group of elements AND 102, the number of the required array (No.Mas) is recorded in register 103. After the information is recorded in the pulse counter 96, through the group of elements AND 97, prepared for opening by the signal from the direct output of the trigger 101, through the group of elements OR 98 it arrives at the output group 35 of block 2. The corresponding information is returned from block 6 through the group of inputs 30 of the block 2 per comparison node 100. Upon receipt of the sync pulse

5, the input 22 of the array search block 2, through the AND 91 element, arrives at the comparison node 100, allowing the comparison of the information recorded in the register 103 and received to the group of inputs 30 of block 2. If the information is not equal, then the trigger 101 remains in the initial state, and the sync pulse delayed by the delay element 92, through the element 93 And enters the record 96 counts in the counter. With the arrival of the next clock pulse, the comparison process is repeated. As soon as the information is compared, the signal from the output of the node 100 of the comparison trigger 101 returns to its original zero position. This will close the group of elements And 97 and the element And 93.

Thus, in the first pulse counter 96, the address of the required array in the library (.) Will be recorded.

If at the output 24 of block 2 there is a signal equivalent to a logical unit from the output of the counter 96 pulses, then this indicates that the entire library has been scanned and there is no required array in block 6. At the same time, the element AND 90 is closed through the element NOT 94, prohibiting the passage of clock pulses. When trigger 101 is in a single state, output 33 of block 2 removes a signal allowing setting the cell address with the initial address of the array to be searched for (Mass) in block 3. When trigger 101 is set to zero, output 31 of block 2 is removed allowing entry to block 7 and output 32 blocks

2 signal allowing modification of the counter.

Block 3 works as follows.

If there is a corresponding signal at the address input 40 of block 3 and a signal. The recording at the control input 42 of the block 3 for processing the array from the data bus 10 through a group of elements 105 and 105 register 109 writes the code corresponding to const 1 and then through the group of elements 108 and 108 into register 110 the code corresponding to const 2 is written. Thus, the adder 111 determines the starting address of the array to be searched for (A | Head)

(A | bibl. + Const 1 Aah. Mas.),

and the second adder 112 determines the final address of the desired array.

(A | con. Mas.)

(A | bi6l. + COnst 1 + Const 2 A | conc.mas.).

In the initial position at the input 48 of block 3 there is a signal equivalent to a logical unit, which prepares the element 113 and the group of elements 115 for the opening.

3 sync pulse, it is through the element And 113, the element OR 118 writes information from the output of the first adder 111 to the pulse counter 116.

As soon as in block 2 the number of the required array in the library is determined, i.e. Since the seventh register 101 returns to the zero state, then a signal is received at the input 49 of the block 3.

equivalent to a logical one, and from the output 48 such a signal is removed. This will lead to the closure of the group of elements And 115 and the element And 113 and preparation for the opening

And 117 elements of the And 120 group of elements. From this moment, the sync pulse through the And 117 element goes to the pulse counter 116, and from the output of the delay element 114, the launch of the comparison node 119.

At the comparison node 119, the information from the output of the second adder 112 (Ayon. Mas.) And the information from the pulse counter 116 is compared. As soon as this information is equal, from the node

119 comparison, a signal equivalent to a logical one is taken. From output 44 of block 3, a signal prohibits the passage of clock pulses, and from output 51 it allows recording (Ayon.mas.) To block 7.

The information from the counter 116 is output to the outputs 45 of block 3 via the And 120 group of elements.

Block 4 works as follows. To write the found array to the block

7, the buffer memory is set to the starting address of the memory area. This information, if there is a corresponding signal at the address input 53 and a control signal Recording at input 43 of block 4,

from the bus 10, the data on the inputs 54 of the block 4 through the group of elements I 122 is fed to the record in the counter 123 pulses. From it, this information on outputs 64 of block 4 enters block 7, preparing the corresponding memory cell to record the first word of the array.

After finding the number of the desired array in block 6 (after flip-over of the trigger 101 in block 2), the input 58 of the information input block 4 receives a signal equivalent to a logical one; preparing a group of elements And 128 for the opening. And information (the first word of the array) from the block

6, corresponding to Ayach. Mas., Through the inputs 59 of the information input unit 4, through the AND 128 group of elements, the OR group of elements 129, the outputs 65 of the information input unit 4 goes to the block 7. When the sync pulse passes through the input 60 of the unit 4, the delay element 130 , element AND 131, element OR 132, output 14 of block 4, this information will be recorded in a memory cell prepared for recording. If the required array is found on

the external media, the recorded information is fed to the inputs 61 of the block 4..

When a clock pulse arrives at input 57, if the array is found in block 6, or at input 62 of block 4, if the array is on external media, the pulse counter 123 is modified, thereby preparing the next memory location for recording.

Once the equalization signal is removed from the comparison node 119 in block 3, i.e. A | con.mas will be detected, which indicates that the entire array has been rewritten, at input 56 of block 4, a signal equivalent to a logical one, prepares the AND 125 element for opening. The delayed clock pulse from the output of the delay element 130 passes through the AND 125 element to the control input of the fourth register 126, allowing the recording of information from the third counter 123 pulses into it. Thus, in the fourth register 126, the address (number) of the memory location in which the last word of the written array is written is written. If necessary, this information is read through the ninth group of elements 127 I to the data bus 10.

Block 5 works as follows.

When searching for an array on an external medium, the corresponding registers in the presence of a signal at address input 158 and the Record at input 157 commands write the beginning of the array, such as an array, first, second, to the corresponding registers of the array allocation node 133 on the external media. the third digit of the array number and the end of reading information from an external medium. The information from the external medium enters the information inputs 11 to the node 113 and to the shift register 134. When a sync pulse arrives at sync input 12, the corresponding comparison nodes, the array allocations included in node 133, compare the received information with codes that have been previously recorded, and the triggers of the shift register 134 store the received information. If an array of type D is searched, then a signal is always removed from the output 140 of the node 133 to the input 147 of the node 135; equivalent to the logical one, and from the output 138 of the node 133 to the input 145 of the node 135, a signal equivalent to a logical zero is recorded. If a type B array is searched for, then opposite signals are taken from these inputs.

After detecting the array type code, output 137 of node 133 to input 144 of node 135 receives a signal which, if there is a delayed clock pulse at output 139, provides for output 150 of four shift pulses, which, when inputted to input 155 of shift register 134, shift information by four digits yes If after the array type code there is a code that does not match the code of the first digit of the array number, then from output 141 of node 133 is removed

Reset signal, which is fed to the input-; 148 node 135 and input 154 of register 134. shift and return the necessary triggers and counters to their initial state. If the following code matches the code of the first digit of the array number, then four shift pulses appear again at output 150.

This happens until the code of the third digit of the number of the array is found; while in register 134, the shift will not be fixed by the sixteen-digit code of the first word of the array passport.

After finding the code of the third digit of the array number at output 163,

5 is a signal that ensures the first word of the passport is overwritten by the outputs 164 in the cell of block 7; the delayed signal from output 162 ensures the formation of the address of the next cell

0 memory, in addition, a signal appears at the input 149, which counts the recorded words of the passport.

After this, the second and third words of the passport are written in the same way. After recording the array passport, the process of recording the array itself begins. The process of writing an array of type D proceeds as described. If a type B array is being rewritten, then not four shift pulses are removed from output 150, but three, and at output 151 a signal equivalent to a logical zero appears, which is fed to input 156 of shift register 134 and blocks information readout to the fourth fourth the entrance.

As soon as the end-of-array code is read, the Stop command is removed from output 160, but if an end-of-read code appears from the external medium, then

0 a signal appears at output 161.

FIG. 7 shows the structure of the desired array located on an external medium. The information in block 7 comes in the form of a hexadecimal code. And

5, the desired array, located on the external medium, can be both of type D and type B. Passports for both types of arrays are constructed and entered in block 7 in the same way. Passport array consists of three words. AT

0 the first word of the array passport is the number of the array, i.e. codes of the type of the array, the first, second and third digits of the array are recorded. In the second word of the array passport, the verification number is recorded (verification volume code). The third word of the array passport contains the checksum of the array.

After the passport on the external carrier the array itself is applied. If on the external carrier an array of type D is applied, i.e. information is read from the four tracks, then

Four lines (four notebooks) correspond to each word in the array. If, on the external carrier, an array of type B is applied, i.e. information is read from only three tracks, then six lines (six triads) correspond to each word of the array. At the end of the array is the code of the end of the array.

In the first mode, the array is searched only on external media, in the second mode, the array is searched only in block 6, in the third mode, the array is searched on external media with the array search continued in block 6, in the fourth mode, the array is searched in block 6 with the array search continued on external media.

For setting the first mode, the operation of the switch 84 is triggered, and the corresponding address and control are set to the inputs 15 and 16. Output 19 in this case removes the Start signal to read the information from the external media. For setting the second mode, the switch 87 is triggered, the corresponding address and control is set to the inputs 15 w.16. In this case, sync pulses are removed from output 20 to search for an array in block 6. To set the third and fourth modes of operation, toggle switches 84 and 87 remain in the off state. In the third operating mode, the signal from output 19 is first removed, and then from output 20. the fourth mode is the opposite.

When operating in the first mode, the readable information from the external medium is fed through information inputs 11 to the comparison circuits of block 5. In comparing devices, the information is compared with the codes recorded previously in the registers of block 5. Recording to the registers is done through inputs 159, 158, 157. finding the array of information from the outputs 164 of the array search block 5 on the external media enters the group of inputs 61 of the block 4 and further through the output 65 into the block 7. If the array is not found and the end reading code of the information on the external media will be read then the stop signal is removed from the output 160 of block 5.

When searching for an array in block 6, the read information on inputs 30 enters block 2. As soon as the address Anach.mas is found. and the address of the masses, then on output 33, the library of block 6 is disconnected, and on output 32, Anac is connected. found array. Now the information from the outputs 30 is fed to the inputs 59 of block 4. As soon as the array is rewritten, i.e. Amas. code is read, then from output 44 to input 23 a signal is received to stop reading the information.

When operating in the third mode, the process of searching for an array from an external medium is similar to the first mode of operation. If an array on an external medium is not found, then when the end reading code for the external media is read from output 161, the signal to the input 21 of the device selection mode selection switch 1 is received. in block 6, further work is similar

0 second mode. When operating in the fourth mode, the signal for switching comes from output 24 to input 18.

Claims (1)

Apparatus of the invention for retrieving information, containing an array search block on an external medium and a buffer memory block, the reset, write, address, receive array and synchronization inputs of the device are connected to the same inputs of the block 0 array search on external media, characterized in that, in order to extend the functionality by searching for information both on external media and in the memory of direct sampling, 5, an array memory block, a mode selection block, an array search block in the array memory, an array transfer block, a control block for transferring from the array memory to a buffer memory are entered, the device reset input is connected to the reset inputs of the mode selection block, search the array in the array array, transfer the array and control the transfer from the array memory to the buffer memory, the device write input is connected to 5 inputs for writing mode select blocks, transferring an array, searching for an array in the array memory, controlling the transfer from the array memory to the buffer memory, the device read input is connected to the read input of the array transfer blocks and the buffer memory, the device address and data inputs are connected respectively, with addresses and data inputs of the first groups of the array search block in the array memory, transmission 5 of the array and control of the transfer from the array memory to the buffer memory, the address inputs of the device addresses are connected to the address inputs of the mode selector block and the address inputs of the first buffer group 0 memory, the first, second and third outputs of the mode setting block are connected respectively to the output of the device nondetecting feature, the start output of the external storage device and the input 5 start-ups of the array search unit in the array memory, the outputs of the first group of which are connected to the data inputs of the second group of the transmission control unit from the array memory to the buffer memory, informational outputs of which are connected to the data inputs of the second group of the array search unit in the array memory, outputs the second group of which is connected to the address inputs of the array memory, whose information outputs are connected to the data inputs of the second group of the array transfer block and the data inputs of the third group of the array search block in the memory Civ, the first, second and third control outputs of which are connected to the inputs of the first, second and third clock signals of the transfer control unit from the array memory to the buffer memory, the first, second and third control outputs of which are connected to the synchronization input of the search block in the memory of the array, the first and second synchronization inputs of the array transfer unit, the outputs of the second group and control are connected to the inputs of the addresses of the second group and the address control input of the buffer memory block, respectively, information output s are connected in $ u Fig.Ј. The fourth, fifth, and sixth control outputs of the array search unit in the array memory are connected to the input of the absence of the array attribute in the array memory of the mode selector unit, the third and fourth synchronization inputs of the transmission block ML xiva, the information outputs of the block array search on external media connected to the data inputs of the third group of the array transfer unit, the outputs of the third group of which are connected to the information outputs of the second group of the device, first to fourth control exhibiting outputs to external storage array search unit connected to the output stop of the external storage device, the undetected feature array to block the external storage medium specifying mode, the fifth and sixth inputs sync array transmission unit, respectively. 3 9 Shut up Fm.ch in 9 iCS 6 & Record KB Cfyoc 165 Reading 6 f9 & € 1 6 ° $ 6 € u // In 9 10 If 1S9 MB W Js & 60 v v v v f v v . . ., j K h h V X lSf i3Ј Phie. 6 Lad / there array Code / Popo liability Cove first tsishry Array g Code Code third digit nocci / fa Check number ( Checksum fJepSoe word j type array End of Pass Code y b 134 iM 5 fe-% J -  : fey  lSf & le i63 76A The first word of the passport array s / jacnopm array Third word f aac / top / no ftaccufa The first word of the type B array AIHUV library A L bibl. .bIvl. A i on h. May. Ai on v. May AJHOV.MOC. AIKOH. May H con May Aj con. May The first array (Amach.mas-Ai / fQH.Moct i-th array (Aituw.Mae. AIMH. May.} J-bsh array (Aj beginning of May. - AJXOHMOC}  Library addresses  At vib. - NImassiba const 1 const Z Zone with initial addresses of arrays At vib. const 1-A1nach.mas. Zone with end addresses of arrays Al5u5s. + Const1 + + const2 ASCON.MOS. Zone recorded arrays